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MipsMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are appended. This helper will facilitate future fixup data structure optimizations.
1 parent 5b7f1c1 commit def731a

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2 files changed

+74
-63
lines changed

2 files changed

+74
-63
lines changed

‎llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -418,7 +418,7 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
418418
{ "fixup_Mips_GPREL16", 0, 16, 0 },
419419
{ "fixup_Mips_LITERAL", 0, 16, 0 },
420420
{ "fixup_Mips_GOT", 0, 16, 0 },
421-
{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
421+
{ "fixup_Mips_PC16", 0, 16, 0 },
422422
{ "fixup_Mips_CALL16", 0, 16, 0 },
423423
{ "fixup_Mips_SHIFT5", 6, 5, 0 },
424424
{ "fixup_Mips_SHIFT6", 6, 5, 0 },
@@ -430,7 +430,7 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
430430
{ "fixup_Mips_TLSLDM", 0, 16, 0 },
431431
{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
432432
{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
433-
{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
433+
{ "fixup_Mips_Branch_PCRel", 0, 16, 0 },
434434
{ "fixup_Mips_GPOFF_HI", 0, 16, 0 },
435435
{ "fixup_MICROMIPS_GPOFF_HI",0, 16, 0 },
436436
{ "fixup_Mips_GPOFF_LO", 0, 16, 0 },
@@ -446,23 +446,23 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
446446
{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
447447
{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
448448
{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
449-
{ "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
450-
{ "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
451-
{ "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
452-
{ "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
453-
{ "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
454-
{ "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
449+
{ "fixup_Mips_PC18_S3", 0, 18, 0 },
450+
{ "fixup_MIPS_PC19_S2", 0, 19, 0 },
451+
{ "fixup_MIPS_PC21_S2", 0, 21, 0 },
452+
{ "fixup_MIPS_PC26_S2", 0, 26, 0 },
453+
{ "fixup_MIPS_PCHI16", 0, 16, 0 },
454+
{ "fixup_MIPS_PCLO16", 0, 16, 0 },
455455
{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
456456
{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
457457
{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
458458
{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
459-
{ "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel },
460-
{ "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
461-
{ "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
462-
{ "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
463-
{ "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
464-
{ "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
465-
{ "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
459+
{ "fixup_MICROMIPS_PC7_S1", 0, 7, 0 },
460+
{ "fixup_MICROMIPS_PC10_S1", 0, 10, 0 },
461+
{ "fixup_MICROMIPS_PC16_S1", 0, 16, 0 },
462+
{ "fixup_MICROMIPS_PC26_S1", 0, 26, 0 },
463+
{ "fixup_MICROMIPS_PC19_S2", 0, 19, 0 },
464+
{ "fixup_MICROMIPS_PC18_S3", 0, 18, 0 },
465+
{ "fixup_MICROMIPS_PC21_S1", 0, 21, 0 },
466466
{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
467467
{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
468468
{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
@@ -504,7 +504,7 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
504504
{ "fixup_Mips_GPREL16", 16, 16, 0 },
505505
{ "fixup_Mips_LITERAL", 16, 16, 0 },
506506
{ "fixup_Mips_GOT", 16, 16, 0 },
507-
{ "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
507+
{ "fixup_Mips_PC16", 16, 16, 0 },
508508
{ "fixup_Mips_CALL16", 16, 16, 0 },
509509
{ "fixup_Mips_SHIFT5", 21, 5, 0 },
510510
{ "fixup_Mips_SHIFT6", 21, 5, 0 },
@@ -516,11 +516,11 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
516516
{ "fixup_Mips_TLSLDM", 16, 16, 0 },
517517
{ "fixup_Mips_DTPREL_HI", 16, 16, 0 },
518518
{ "fixup_Mips_DTPREL_LO", 16, 16, 0 },
519-
{ "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
519+
{ "fixup_Mips_Branch_PCRel",16, 16, 0 },
520520
{ "fixup_Mips_GPOFF_HI", 16, 16, 0 },
521-
{ "fixup_MICROMIPS_GPOFF_HI", 16, 16, 0 },
521+
{ "fixup_MICROMIPS_GPOFF_HI", 16, 16, 0 },
522522
{ "fixup_Mips_GPOFF_LO", 16, 16, 0 },
523-
{ "fixup_MICROMIPS_GPOFF_LO", 16, 16, 0 },
523+
{ "fixup_MICROMIPS_GPOFF_LO", 16, 16, 0 },
524524
{ "fixup_Mips_GOT_PAGE", 16, 16, 0 },
525525
{ "fixup_Mips_GOT_OFST", 16, 16, 0 },
526526
{ "fixup_Mips_GOT_DISP", 16, 16, 0 },
@@ -532,23 +532,23 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
532532
{ "fixup_Mips_GOT_LO16", 16, 16, 0 },
533533
{ "fixup_Mips_CALL_HI16", 16, 16, 0 },
534534
{ "fixup_Mips_CALL_LO16", 16, 16, 0 },
535-
{ "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel },
536-
{ "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
537-
{ "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
538-
{ "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
539-
{ "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
540-
{ "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
535+
{ "fixup_Mips_PC18_S3", 14, 18, 0 },
536+
{ "fixup_MIPS_PC19_S2", 13, 19, 0 },
537+
{ "fixup_MIPS_PC21_S2", 11, 21, 0 },
538+
{ "fixup_MIPS_PC26_S2", 6, 26, 0 },
539+
{ "fixup_MIPS_PCHI16", 16, 16, 0 },
540+
{ "fixup_MIPS_PCLO16", 16, 16, 0 },
541541
{ "fixup_MICROMIPS_26_S1", 6, 26, 0 },
542542
{ "fixup_MICROMIPS_HI16", 16, 16, 0 },
543543
{ "fixup_MICROMIPS_LO16", 16, 16, 0 },
544544
{ "fixup_MICROMIPS_GOT16", 16, 16, 0 },
545-
{ "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel },
546-
{ "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel },
547-
{ "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
548-
{ "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
549-
{ "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel },
550-
{ "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel },
551-
{ "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel },
545+
{ "fixup_MICROMIPS_PC7_S1", 9, 7, 0 },
546+
{ "fixup_MICROMIPS_PC10_S1", 6, 10, 0 },
547+
{ "fixup_MICROMIPS_PC16_S1",16, 16, 0 },
548+
{ "fixup_MICROMIPS_PC26_S1", 6, 26, 0 },
549+
{ "fixup_MICROMIPS_PC19_S2",13, 19, 0 },
550+
{ "fixup_MICROMIPS_PC18_S3",14, 18, 0 },
551+
{ "fixup_MICROMIPS_PC21_S1",11, 21, 0 },
552552
{ "fixup_MICROMIPS_CALL16", 16, 16, 0 },
553553
{ "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
554554
{ "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

Lines changed: 42 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,30 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
5555

5656
} // end namespace llvm
5757

58+
static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
59+
const MCExpr *Value, uint16_t Kind) {
60+
bool PCRel = false;
61+
switch (Kind) {
62+
case Mips::fixup_Mips_PC16:
63+
case Mips::fixup_Mips_Branch_PCRel:
64+
case Mips::fixup_MIPS_PC18_S3:
65+
case Mips::fixup_MIPS_PC19_S2:
66+
case Mips::fixup_MIPS_PC21_S2:
67+
case Mips::fixup_MIPS_PC26_S2:
68+
case Mips::fixup_MIPS_PCHI16:
69+
case Mips::fixup_MIPS_PCLO16:
70+
case Mips::fixup_MICROMIPS_PC7_S1:
71+
case Mips::fixup_MICROMIPS_PC10_S1:
72+
case Mips::fixup_MICROMIPS_PC16_S1:
73+
case Mips::fixup_MICROMIPS_PC26_S1:
74+
case Mips::fixup_MICROMIPS_PC19_S2:
75+
case Mips::fixup_MICROMIPS_PC18_S3:
76+
case Mips::fixup_MICROMIPS_PC21_S1:
77+
PCRel = true;
78+
}
79+
Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
80+
}
81+
5882
// If the D<shift> instruction has a shift amount that is greater
5983
// than 31 (checked in calling routine), lower it to a D<shift>32 instruction
6084
static void LowerLargeShift(MCInst& Inst) {
@@ -236,8 +260,7 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
236260

237261
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
238262
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
239-
Fixups.push_back(MCFixup::create(0, FixupExpression,
240-
MCFixupKind(Mips::fixup_Mips_PC16)));
263+
addFixup(Fixups, 0, FixupExpression, Mips::fixup_Mips_PC16);
241264
return 0;
242265
}
243266

@@ -258,8 +281,7 @@ getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
258281

259282
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
260283
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
261-
Fixups.push_back(MCFixup::create(0, FixupExpression,
262-
MCFixupKind(Mips::fixup_Mips_PC16)));
284+
addFixup(Fixups, 0, FixupExpression, Mips::fixup_Mips_PC16);
263285
return 0;
264286
}
265287

@@ -281,8 +303,7 @@ getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
281303

282304
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
283305
MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
284-
Fixups.push_back(MCFixup::create(0, FixupExpression,
285-
MCFixupKind(Mips::fixup_Mips_PC16)));
306+
addFixup(Fixups, 0, FixupExpression, Mips::fixup_Mips_PC16);
286307
return 0;
287308
}
288309

@@ -304,8 +325,7 @@ getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
304325

305326
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
306327
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
307-
Fixups.push_back(MCFixup::create(0, FixupExpression,
308-
MCFixupKind(Mips::fixup_Mips_PC16)));
328+
addFixup(Fixups, 0, FixupExpression, Mips::fixup_Mips_PC16);
309329
return 0;
310330
}
311331

@@ -325,8 +345,7 @@ getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
325345
"getBranchTargetOpValueMM expects only expressions or immediates");
326346

327347
const MCExpr *Expr = MO.getExpr();
328-
Fixups.push_back(MCFixup::create(0, Expr,
329-
MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
348+
addFixup(Fixups, 0, Expr, Mips::fixup_MICROMIPS_PC7_S1);
330349
return 0;
331350
}
332351

@@ -346,8 +365,7 @@ getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
346365
"getBranchTargetOpValuePC10 expects only expressions or immediates");
347366

348367
const MCExpr *Expr = MO.getExpr();
349-
Fixups.push_back(MCFixup::create(0, Expr,
350-
MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
368+
addFixup(Fixups, 0, Expr, Mips::fixup_MICROMIPS_PC10_S1);
351369
return 0;
352370
}
353371

@@ -367,7 +385,7 @@ getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
367385
"getBranchTargetOpValueMM expects only expressions or immediates");
368386

369387
const MCExpr *Expr = MO.getExpr();
370-
Fixups.push_back(MCFixup::create(0, Expr, Mips::fixup_MICROMIPS_PC16_S1));
388+
addFixup(Fixups, 0, Expr, Mips::fixup_MICROMIPS_PC16_S1);
371389
return 0;
372390
}
373391

@@ -388,8 +406,7 @@ getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
388406

389407
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
390408
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
391-
Fixups.push_back(
392-
MCFixup::create(0, FixupExpression, Mips::fixup_MIPS_PC21_S2));
409+
addFixup(Fixups, 0, FixupExpression, Mips::fixup_MIPS_PC21_S2);
393410
return 0;
394411
}
395412

@@ -410,8 +427,7 @@ getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
410427

411428
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
412429
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
413-
Fixups.push_back(
414-
MCFixup::create(0, FixupExpression, Mips::fixup_MICROMIPS_PC21_S1));
430+
addFixup(Fixups, 0, FixupExpression, Mips::fixup_MICROMIPS_PC21_S1);
415431
return 0;
416432
}
417433

@@ -432,8 +448,7 @@ getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
432448

433449
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
434450
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
435-
Fixups.push_back(
436-
MCFixup::create(0, FixupExpression, Mips::fixup_MIPS_PC26_S2));
451+
addFixup(Fixups, 0, FixupExpression, Mips::fixup_MIPS_PC26_S2);
437452
return 0;
438453
}
439454

@@ -454,8 +469,7 @@ unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
454469

455470
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
456471
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
457-
Fixups.push_back(MCFixup::create(0, FixupExpression,
458-
MCFixupKind(Mips::fixup_MICROMIPS_PC26_S1)));
472+
addFixup(Fixups, 0, FixupExpression, Mips::fixup_MICROMIPS_PC26_S1);
459473
return 0;
460474
}
461475

@@ -476,7 +490,7 @@ getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
476490
const MCExpr *Expr = MO.getExpr();
477491
Mips::Fixups FixupKind =
478492
isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 : Mips::fixup_Mips_LO16;
479-
Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
493+
addFixup(Fixups, 0, Expr, MCFixupKind(FixupKind));
480494
return 0;
481495
}
482496

@@ -495,8 +509,7 @@ getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
495509
"getJumpTargetOpValue expects only expressions or an immediate");
496510

497511
const MCExpr *Expr = MO.getExpr();
498-
Fixups.push_back(MCFixup::create(0, Expr,
499-
MCFixupKind(Mips::fixup_Mips_26)));
512+
addFixup(Fixups, 0, Expr, Mips::fixup_Mips_26);
500513
return 0;
501514
}
502515

@@ -512,8 +525,7 @@ getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
512525
"getJumpTargetOpValueMM expects only expressions or an immediate");
513526

514527
const MCExpr *Expr = MO.getExpr();
515-
Fixups.push_back(MCFixup::create(0, Expr,
516-
MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
528+
addFixup(Fixups, 0, Expr, Mips::fixup_MICROMIPS_26_S1);
517529
return 0;
518530
}
519531

@@ -691,7 +703,7 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
691703
isMicroMips(STI) ? Mips::fixup_MICROMIPS_SUB : Mips::fixup_Mips_SUB;
692704
break;
693705
}
694-
Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
706+
addFixup(Fixups, 0, MipsExpr, MCFixupKind(FixupKind));
695707
return 0;
696708
}
697709

@@ -732,8 +744,7 @@ unsigned MipsMCCodeEmitter::getImmOpValue(const MCInst &MI, const MCOperand &MO,
732744
return Res;
733745
unsigned MIFrm = MipsII::getFormat(MCII.get(MI.getOpcode()).TSFlags);
734746
if (!isa<MCSpecifierExpr>(Expr) && MIFrm == MipsII::FrmI) {
735-
Fixups.push_back(
736-
MCFixup::create(0, Expr, MCFixupKind(Mips::fixup_Mips_AnyImm16)));
747+
addFixup(Fixups, 0, Expr, MCFixupKind(Mips::fixup_Mips_AnyImm16));
737748
return 0;
738749
}
739750
return getExprOpValue(Expr, Fixups, STI);
@@ -962,7 +973,7 @@ MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
962973
const MCExpr *Expr = MO.getExpr();
963974
Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2
964975
: Mips::fixup_MIPS_PC19_S2;
965-
Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
976+
addFixup(Fixups, 0, Expr, MCFixupKind(FixupKind));
966977
return 0;
967978
}
968979

@@ -984,7 +995,7 @@ MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
984995
const MCExpr *Expr = MO.getExpr();
985996
Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
986997
: Mips::fixup_MIPS_PC18_S3;
987-
Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
998+
addFixup(Fixups, 0, Expr, MCFixupKind(FixupKind));
988999
return 0;
9891000
}
9901001

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