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SPARC: Start moving runtime libcall config to tablegen
1 parent 1a0e627 commit 38bfe36

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2 files changed

+16
-13
lines changed

2 files changed

+16
-13
lines changed

llvm/include/llvm/IR/RuntimeLibcalls.td

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Original file line numberDiff line numberDiff line change
@@ -1828,6 +1828,22 @@ def _Q_qtoull : RuntimeLibcallImpl<FPTOUINT_F128_I64>;
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def _Q_lltoq : RuntimeLibcallImpl<SINTTOFP_I64_F128>;
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def _Q_ulltoq : RuntimeLibcallImpl<UINTTOFP_I64_F128>;
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def isSPARC : RuntimeLibcallPredicate<"TT.isSPARC()">;
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def isSPARC32 : RuntimeLibcallPredicate<"TT.isSPARC32()">;
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def isSPARC64 : RuntimeLibcallPredicate<"TT.isSPARC64()">;
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defvar SPARC64_MulDivCalls = [
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__mulsi3, __divsi3, __modsi3, __udivsi3, __umodsi3
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];
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def SPARCSystemLibrary
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: SystemRuntimeLibrary<isSPARC,
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(add (sub DefaultLibcallImpls32, SPARC64_MulDivCalls),
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sparc_umul, sparc_div, sparc_udiv, sparc_rem, sparc_urem,
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LibcallImpls<(add _Q_qtoll, _Q_qtoull, _Q_lltoq, _Q_ulltoq), isSPARC32>,
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LibcallImpls<(add SPARC64_MulDivCalls, Int128RTLibcalls), isSPARC64>)
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>;
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//===----------------------------------------------------------------------===//
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// Windows Runtime Libcalls
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//===----------------------------------------------------------------------===//

llvm/lib/Target/Sparc/SparcISelLowering.cpp

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1824,12 +1824,6 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::MULHS, MVT::i32, Expand);
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setOperationAction(ISD::MUL, MVT::i32, Expand);
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setLibcallImpl(RTLIB::MUL_I32, RTLIB::sparc_umul);
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setLibcallImpl(RTLIB::SDIV_I32, RTLIB::sparc_div);
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setLibcallImpl(RTLIB::UDIV_I32, RTLIB::sparc_udiv);
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setLibcallImpl(RTLIB::SREM_I32, RTLIB::sparc_rem);
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setLibcallImpl(RTLIB::UREM_I32, RTLIB::sparc_urem);
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if (Subtarget->useSoftMulDiv()) {
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// .umul works for both signed and unsigned
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
@@ -1879,13 +1873,6 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::STORE, MVT::f128, Custom);
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}
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if (!Subtarget->is64Bit()) {
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setLibcallImpl(RTLIB::FPTOSINT_F128_I64, RTLIB::_Q_qtoll);
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setLibcallImpl(RTLIB::FPTOUINT_F128_I64, RTLIB::_Q_qtoull);
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setLibcallImpl(RTLIB::SINTTOFP_I64_F128, RTLIB::_Q_lltoq);
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setLibcallImpl(RTLIB::UINTTOFP_I64_F128, RTLIB::_Q_ulltoq);
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}
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if (Subtarget->hasHardQuad()) {
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setOperationAction(ISD::FADD, MVT::f128, Legal);
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setOperationAction(ISD::FSUB, MVT::f128, Legal);

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