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[CodeGen] Use Register::id() to avoid implicit cast. NFC
1 parent e56215d commit 13cce8c

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8 files changed

+11
-9
lines changed

8 files changed

+11
-9
lines changed

llvm/include/llvm/CodeGen/RegisterPressure.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ class LiveRegSet {
280280
if (Reg.isVirtual())
281281
return Reg.virtRegIndex() + NumRegUnits;
282282
assert(Reg < NumRegUnits);
283-
return Reg;
283+
return Reg.id();
284284
}
285285

286286
Register getRegFromSparseIndex(unsigned SparseIndex) const {

llvm/lib/CodeGen/BranchFolding.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -264,7 +264,7 @@ static unsigned HashMachineInstr(const MachineInstr &MI) {
264264
unsigned OperandHash = 0;
265265
switch (Op.getType()) {
266266
case MachineOperand::MO_Register:
267-
OperandHash = Op.getReg();
267+
OperandHash = Op.getReg().id();
268268
break;
269269
case MachineOperand::MO_Immediate:
270270
OperandHash = Op.getImm();

llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -358,7 +358,9 @@ class StatepointState {
358358
MachineBasicBlock *getEHPad() const { return EHPad; }
359359

360360
// Return true if register is callee saved.
361-
bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; }
361+
bool isCalleeSaved(Register Reg) {
362+
return (Mask[Reg.id() / 32] >> (Reg.id() % 32)) & 1;
363+
}
362364

363365
// Iterates over statepoint meta args to find caller saver registers.
364366
// Also cache the size of found registers.

llvm/lib/CodeGen/MIRParser/MIParser.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2828,7 +2828,7 @@ bool MIParser::parseCustomRegisterMaskOperand(MachineOperand &Dest) {
28282828
if (parseNamedRegister(Reg))
28292829
return true;
28302830
lex();
2831-
Mask[Reg / 32] |= 1U << (Reg % 32);
2831+
Mask[Reg.id() / 32] |= 1U << (Reg.id() % 32);
28322832
}
28332833

28342834
// TODO: Report an error if the same register is used more than once.
@@ -2853,7 +2853,7 @@ bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
28532853
if (parseNamedRegister(Reg))
28542854
return true;
28552855
lex();
2856-
Mask[Reg / 32] |= 1U << (Reg % 32);
2856+
Mask[Reg.id() / 32] |= 1U << (Reg.id() % 32);
28572857
// TODO: Report an error if the same register is used more than once.
28582858
if (Token.isNot(MIToken::comma))
28592859
break;

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -751,7 +751,7 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
751751
Register Reg;
752752
if (parseNamedRegisterReference(PFS, Reg, RegSource.Value, Error))
753753
return error(Error, RegSource.SourceRange);
754-
CalleeSavedRegisters.push_back(Reg);
754+
CalleeSavedRegisters.push_back(Reg.id());
755755
}
756756
RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
757757
}

llvm/lib/CodeGen/RegAllocGreedy.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -443,7 +443,7 @@ void RAGreedy::enqueue(PQueue &CurQueue, const LiveInterval *LI) {
443443

444444
// The virtual register number is a tie breaker for same-sized ranges.
445445
// Give lower vreg numbers higher priority to assign them first.
446-
CurQueue.push(std::make_pair(Ret, ~Reg));
446+
CurQueue.push(std::make_pair(Ret, ~Reg.id()));
447447
}
448448

449449
unsigned DefaultPriorityAdvisor::getPriority(const LiveInterval &LI) const {

llvm/lib/CodeGen/RegisterCoalescer.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2311,7 +2311,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
23112311
// We must also check for overlaps with regmask clobbers.
23122312
BitVector RegMaskUsable;
23132313
if (LIS->checkRegMaskInterference(RHS, RegMaskUsable) &&
2314-
!RegMaskUsable.test(DstReg)) {
2314+
!RegMaskUsable.test(DstReg.id())) {
23152315
LLVM_DEBUG(dbgs() << "\t\tRegMask interference\n");
23162316
return false;
23172317
}

llvm/lib/CodeGen/RegisterScavenging.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
112112
BitVector Mask(TRI->getNumRegs());
113113
for (Register Reg : *RC)
114114
if (!isRegUsed(Reg))
115-
Mask.set(Reg);
115+
Mask.set(Reg.id());
116116
return Mask;
117117
}
118118

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