Remove single state restriction on FSM to SV #8665
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The conversion seems to work and gets to Verilog. It seems correct, if not most efficient lowered form if there is only one state. Not sure if there was a different reason for this restriction (beyond, this would be better as just HWModule, although didn't see a pattern that would do that).
teqdruid
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Jul 8, 2025
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The conversion seems to work and gets to Verilog. It seems correct, if not most efficient lowered form if there is only one state. Not sure if there was a different reason for this restriction (beyond, this would be better as just HWModule, although didn't see a pattern that would do that).