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Merged
merged 2 commits into from
Jun 26, 2025
Merged

master: add irq #85

merged 2 commits into from
Jun 26, 2025

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maass-hamburg
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@maass-hamburg maass-hamburg commented Jun 2, 2025

  • add irq for the master

  • add a wrapper for the phy and the core, so they will only use one csr.

implementation for zephyr: zephyrproject-rtos/zephyr#91050

add interrupt for rx_ready.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
add a wrapper for the phy and the core, so they
will only use one csr.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
@maass-hamburg maass-hamburg marked this pull request as ready for review June 2, 2025 11:54
@maass-hamburg
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@enjoy-digital please take a look

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enjoy-digital commented Jun 26, 2025

Thanks @maass-hamburg, I already had a first look. This looks fine. I just need to think a bit about the Wrapper to try to have a consistent approach between the different cores where PHY also generally have use their own CSR. I'm not saying current approach is better, but just need to think a bit to have things consistent. I'll try to have a closer look tomorrow.

@enjoy-digital
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@maass-hamburg: I think we can merge. For the LiteSPIWrapper integration (and enjoy-digital/litex#2253), I'll just think a bit.

@enjoy-digital enjoy-digital merged commit 3294479 into litex-hub:master Jun 26, 2025
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@maass-hamburg
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@maass-hamburg: I think we can merge. For the LiteSPIWrapper integration (and enjoy-digital/litex#2253), I'll just think a bit.

@enjoy-digital maybe it helps to orient us at the device trees that linux and zephyr use. If it's one node on the device tree, it should be one CSR. Or if it is needed to implement one api implementation. separate CSRs that only have a register to set the speed or the clock divider should therefore be part of the 'main' device csr. Only for liteeth it makes sense to have it separated, because the phy there contains the mdio or for 1000Base-X the registers for the link speed and state and zephyr and linux have a seperate ethernet-controller and mdio and ethernet phy.

@maass-hamburg maass-hamburg deleted the add_irq branch June 26, 2025 20:22
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@maass-hamburg: I agree it's better to only have one CSR per peripheral. But I also want for now to keep the PHY+Core integration in the LiteX's add_xxyy methods (for consistency for now, in the long term it could be good to have the add_xxyy methods directly in the Cores repository).

Could you have a look at enjoy-digital/litex@272f024?

It keeps the integration almost similar in LiteX and avoids the LiteSPIWrapper, from:

└─── spiflash_phy (LiteSPIPHY)
│    └─── spiflash_phy (LiteSPIDDRPHYCore)
│    │    └─── clkgen (DDRLiteSPIClkGen)
│    │    └─── cs_control (LiteSPICSControl)
│    │    │    └─── timer (WaitTimer)
│    │    └─── fsm (FSM)
└─── spiflash_core (LiteSPI)
│    └─── crossbar (LiteSPICrossbar)
│    │    └─── rr (RoundRobin)
│    │    └─── tx_mux (Multiplexer)
│    │    └─── rx_demux (Demultiplexer)
│    └─── mmap (LiteSPIMMAP)
│    │    └─── burst_timeout (WaitTimer)
│    │    └─── fsm (FSM)
│    └─── master (LiteSPIMaster)
│    │    └─── tx_fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    └─── rx_fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)

we now get:

└─── spiflash (LiteSPI)
│    └─── crossbar (LiteSPICrossbar)
│    │    └─── rr (RoundRobin)
│    │    └─── tx_mux (Multiplexer)
│    │    └─── rx_demux (Demultiplexer)
│    └─── mmap (LiteSPIMMAP)
│    │    └─── burst_timeout (WaitTimer)
│    │    └─── fsm (FSM)
│    └─── master (LiteSPIMaster)
│    │    └─── tx_fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    └─── rx_fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    └─── phy (LiteSPIPHY)
│    │    └─── spiflash_phy (LiteSPIDDRPHYCore)
│    │    │    └─── clkgen (DDRLiteSPIClkGen)
│    │    │    └─── cs_control (LiteSPICSControl)
│    │    │    │    └─── timer (WaitTimer)
│    │    │    └─── fsm (FSM)

and the CSRs of the PHY will now directly use the CSR slot of the Core.

If it sounds good to you, can you update enjoy-digital/litex#2253 with this and with the IRQ support, or do you want me to do it?

@maass-hamburg
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If it sounds good to you, can you update enjoy-digital/litex#2253 with this and with the IRQ support, or do you want me to do it?

changed it, including the bios weith now no longer needs the _core and _CORE in the CSR defines and functions

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Thanks for the update @maass-hamburg, with 47adbe1, I removed the wrapper since think it's no longer useful.

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