coreboot-nitrokey: update dasharo to v1.7.2

* remove all previous coreboot patches (as they are already included)
* to be investigated: linux trampoline patch
* add new patch to hardcode sleep configuration
* activate smmstore as dasharo vendor code requires it

Signed-off-by: Markus Meissner <coder@safemailbox.de>

Author: daringer

config/coreboot-nitropad-ns50.config

@@ -560,7 +560,7 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
 # CONFIG_ELOG is not set
 CONFIG_CACHE_MRC_SETTINGS=y
 CONFIG_MRC_SETTINGS_PROTECT=y
-# CONFIG_SMMSTORE is not set
+CONFIG_SMMSTORE=y
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y

config/coreboot-nitropad-nv41.config

@@ -560,7 +560,7 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
 # CONFIG_ELOG is not set
 CONFIG_CACHE_MRC_SETTINGS=y
 CONFIG_MRC_SETTINGS_PROTECT=y
-# CONFIG_SMMSTORE is not set
+CONFIG_SMMSTORE=y
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y

modules/coreboot

@@ -88,7 +88,7 @@ $(eval $(call coreboot_module,purism,))
 #Nitrokey nv41/ns50 are based on Dasharo coreboot port,
 # with patches staging under coreboot-clevo_release
 coreboot-nitrokey_repo := https://github.com/dasharo/coreboot
-coreboot-nitrokey_commit_hash := ae10b20f5c6abc9c23f709b65c46be6525da8c13
+coreboot-nitrokey_commit_hash := 1bcb338682b612cfcca8bba02846f78139b2e0c8
 coreboot-nitrokey_patch_version := clevo_release
 #We use clevo_release's crossgcc for now, unshared but between nitropad nv41/ns50
 $(eval $(call coreboot_module,nitrokey,))

patches/coreboot-nitrokey-clevo_release/0001-change_acpica-unix2_location_to_a_mirror.patch

@@ -0,0 +1,16 @@
+diff -ur dasharo_cb.org/src/vendorcode/dasharo/options.c dasharo_cb/src/vendorcode/dasharo/options.c
+--- dasharo_cb.org/src/vendorcode/dasharo/options.c	2023-12-18 21:57:46.915582991 +0100
++++ dasharo_cb/src/vendorcode/dasharo/options.c	2023-12-19 19:16:13.077019389 +0100
+@@ -189,7 +189,12 @@
+ 
+ uint8_t get_sleep_type_option(void)
+ {
++
++#if CONFIG(BOARD_NOVACUSTOM_NV4X_ADLP)
++	uint8_t sleep_type = SLEEP_TYPE_OPTION_S3;
++#else
+ 	uint8_t sleep_type = SLEEP_TYPE_OPTION_S0IX;
++#endif
+ 
+ 	if (CONFIG(DRIVERS_EFI_VARIABLE_STORE))
+ 		read_u8_var("SleepType", &sleep_type);