💡 My solutions to the Verilog-based problem set on HDLBits — 182 problems covering combinational, sequential, and FSM-based digital design.
HDLBits is an interactive platform developed by Henry Wong at University of Toronto to help students and engineers master Verilog HDL through progressively challenging problems. It focuses on:
- ✅ Syntax and simulation basics
- ✅ Combinational and sequential logic design
- ✅ Finite State Machines (Mealy & Moore)
- ✅ Common design patterns like shift registers and counters
- ✅ Debugging and waveform analysis
All problems encourage correct synthesizable Verilog practices.
🟢 Completed all 182 problems!
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HDLBits_Solutions/
├── 0. Getting Started/
├── 1. Verilog Language/
│ ├── 1 - Basics/
│ ├── 2 - Vectors/
│ ├── 3 - Modules Hierarchy/
│ ├── 4 - Procedures/
│ └── 5 - More Verilog Features/
├── 2. Circuits/
│ ├── 1 - Combinational Logic/
│ ├── 2 - Sequential Logic/
│ └── 3 - Building Larger Circuits/
├── 3. Verification - Reading Simulations/
│ ├── 1 - Finding bugs in code/
│ └── 2 - Build a circuit from a simulation waveform/
├── 4. Verification - Writing Testbenches/
└── 5. CS450/
Special thanks to my friend andbhavyaa for creating ⚡︎ skeldir — a command-line tool that automatically generates folder skeletons (directory + file structures) based on text templates.
By combining ChatGPT to generate the structured folder layout and skeldir to create it instantly on my file system, I was able to set up all problem folders and files without any manual effort.
⚡ The entire process was hassle-free and saved lots of repetitive work!
If you're working on projects that require bulk folder or file setup, I highly recommend checking it out.
If you have any ideas, just open an issue and tell me what you think!
Whether it's improving solutions, adding new waveform visualizations, fixing typos, or enhancing the documentation — every bit helps!