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josevcmjosevcm
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Merge pull request #52 from josevcm/develop
Add pending DSL devices
2 parents 30ee028 + 95750fb commit 533505a

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6 files changed

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-4
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6 files changed

+117
-4
lines changed

‎.github/workflows/cmake-ubuntu.yml

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push:
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tags:
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- '*' # any tag
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branches:
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- master
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# branches:
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# - master
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jobs:
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build:

‎.github/workflows/cmake-windows.yml

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Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@ on:
44
push:
55
tags:
66
- '*' # any tag
7-
branches:
8-
- master
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# branches:
8+
# - master
99

1010
jobs:
1111
build:

‎dat/firmware/DSLogicPlus-pgl12-2.bin

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‎dat/firmware/DSLogicU2Basic-pgl12-2.bin

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‎dat/firmware/DSLogicU2Basic-pgl12.bin

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‎src/nfc-lib/lib-hw/hw-logic/src/main/cpp/DSLogicInternal.h

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@@ -1162,6 +1162,119 @@ static const dsl_profile dsl_profiles[] = {
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.quarter_samplerate = DSL_MHZ(400), // quarter_samplerate
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},
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},
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{
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0x2A0E,
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0x0031,
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LIBUSB_SPEED_HIGH,
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"DreamSourceLab",
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"DSLogic U2Basic",
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nullptr,
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"DSLogicU2Basic.fw",
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"DSLogicU2Basic-pgl12.bin",
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"DSLogicU2Basic-pgl12.bin",
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.dev_caps {
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.mode_caps = CAPS_MODE_LOGIC, // mode_caps
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.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_MAX25_VTH | CAPS_FEATURE_SECURITY, // feature_caps
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.channels = DSL_CH(DSLogicDevice::DSL_STREAM20x16) |
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DSL_CH(DSLogicDevice::DSL_STREAM25x12) |
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DSL_CH(DSLogicDevice::DSL_STREAM50x6) |
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DSL_CH(DSLogicDevice::DSL_STREAM100x3) |
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DSL_CH(DSLogicDevice::DSL_BUFFER100x16), // channels
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.total_ch_num = 16, // total_ch_num
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.hw_depth = DSL_MB(64), // hw_depth
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.dso_depth = 0, // dso_depth
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.intest_channel = DSLogicDevice::DSL_BUFFER100x16, // intest_channel
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.vdivs = nullptr, // vdivs
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.samplerates = samplerates100, // samplerates
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.vga_id = 0x00, // vga_id
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.default_channelid = DSLogicDevice::DSL_STREAM50x6, // default_channelid
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.default_samplerate = DSL_MHZ(1), // default_samplerate
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.default_samplelimit = DSL_Mn(1), // default_samplelimit
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.default_pwmtrans = 0x0000, // default_pwmtrans
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.default_pwmmargin = 0x0000, // default_pwmmargin
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.ref_min = 0x00000000, // ref_min
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.ref_max = 0x00000000, // ref_max
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.default_comb_comp = 0x00, // default_comb_comp
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.half_samplerate = DSL_MHZ(200), // half_samplerate
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.quarter_samplerate = DSL_MHZ(400), // quarter_samplerate
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}
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},
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{
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0x2A0E,
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0x0034,
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LIBUSB_SPEED_HIGH,
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"DreamSourceLab",
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"DSLogic PLus",
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nullptr,
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"DSLogicPlus-pgl12-2.fw",
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"DSLogicPlus-pgl12-2.bin",
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"DSLogicPlus-pgl12-2.bin",
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.dev_caps {
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.mode_caps = CAPS_MODE_LOGIC, // mode_caps
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.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_MAX25_VTH | CAPS_FEATURE_SECURITY, // feature_caps
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.channels = DSL_CH(DSLogicDevice::DSL_STREAM20x16) |
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DSL_CH(DSLogicDevice::DSL_STREAM25x12) |
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DSL_CH(DSLogicDevice::DSL_STREAM50x6) |
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DSL_CH(DSLogicDevice::DSL_STREAM100x3) |
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DSL_CH(DSLogicDevice::DSL_BUFFER100x16) |
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DSL_CH(DSLogicDevice::DSL_BUFFER200x8) |
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DSL_CH(DSLogicDevice::DSL_BUFFER400x4), // channels
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.total_ch_num = 16, // total_ch_num
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.hw_depth = DSL_MB(256), // hw_depth
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.dso_depth = 0, // dso_depth
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.intest_channel = DSLogicDevice::DSL_BUFFER100x16, // intest_channel
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.vdivs = nullptr, // vdivs
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.samplerates = samplerates400, // samplerates
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.vga_id = 0x00, // vga_id
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.default_channelid = DSLogicDevice::DSL_STREAM50x6, // default_channelid
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.default_samplerate = DSL_MHZ(1), // default_samplerate
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.default_samplelimit = DSL_Mn(1), // default_samplelimit
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.default_pwmtrans = 0x0000, // default_pwmtrans
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.default_pwmmargin = 0x0000, // default_pwmmargin
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.ref_min = 0x00000000, // ref_min
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.ref_max = 0x00000000, // ref_max
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.default_comb_comp = 0x00, // default_comb_comp
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.half_samplerate = DSL_MHZ(200), // half_samplerate
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.quarter_samplerate = DSL_MHZ(400), // quarter_samplerate
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}
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},
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{
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0x2A0E,
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0x0035,
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LIBUSB_SPEED_HIGH,
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"DreamSourceLab",
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"DSLogic U2Basic",
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nullptr,
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"DSLogicU2Basic-pgl12-2.fw",
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"DSLogicU2Basic-pgl12-2.bin",
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"DSLogicU2Basic-pgl12-2.bin",
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.dev_caps {
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.mode_caps = CAPS_MODE_LOGIC, // mode_caps
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.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_MAX25_VTH | CAPS_FEATURE_SECURITY, // feature_caps
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.channels = DSL_CH(DSLogicDevice::DSL_STREAM20x16) |
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DSL_CH(DSLogicDevice::DSL_STREAM25x12) |
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DSL_CH(DSLogicDevice::DSL_STREAM50x6) |
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DSL_CH(DSLogicDevice::DSL_STREAM100x3) |
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DSL_CH(DSLogicDevice::DSL_BUFFER100x16), // channels
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.total_ch_num = 16, // total_ch_num
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.hw_depth = DSL_MB(64), // hw_depth
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.dso_depth = 0, // dso_depth
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.intest_channel = DSLogicDevice::DSL_BUFFER100x16, // intest_channel
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.vdivs = nullptr, // vdivs
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.samplerates = samplerates100, // samplerates
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.vga_id = 0x00, // vga_id
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.default_channelid = DSLogicDevice::DSL_STREAM50x6, // default_channelid
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.default_samplerate = DSL_MHZ(1), // default_samplerate
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.default_samplelimit = DSL_Mn(1), // default_samplelimit
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.default_pwmtrans = 0x0000, // default_pwmtrans
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.default_pwmmargin = 0x0000, // default_pwmmargin
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.ref_min = 0x00000000, // ref_min
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.ref_max = 0x00000000, // ref_max
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.default_comb_comp = 0x00, // default_comb_comp
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.half_samplerate = DSL_MHZ(200), // half_samplerate
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.quarter_samplerate = DSL_MHZ(400), // quarter_samplerate
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}
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},
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{}
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};
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