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josevcmjosevcm
authored
Merge pull request #51
add support for: DSLogic Basic,U2Basic, U3Basic, Plus, U2Pro
2 parents 5659e84 + 90f44b7 commit 30ee028

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5 files changed

+264
-81
lines changed

5 files changed

+264
-81
lines changed

‎dat/firmware/DSLogicBasic.bin

333 KB
Binary file not shown.

‎dat/firmware/DSLogicPlus.bin

333 KB
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‎dat/firmware/DSLogicU2Basic.bin

333 KB
Binary file not shown.

‎dat/firmware/DSLogicU2Pro16.bin

454 KB
Binary file not shown.

‎src/nfc-lib/lib-hw/hw-logic/src/main/cpp/DSLogicInternal.h

Lines changed: 264 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -397,7 +397,7 @@ struct dsl_caps
397397
int dso_depth;
398398
int intest_channel;
399399
const long *vdivs;
400-
const long *samplerates;
400+
const unsigned long long *samplerates;
401401
int vga_id;
402402
int default_channelid;
403403
long default_samplerate;
@@ -593,7 +593,37 @@ static const char *probe_units[] = {
593593
"m/s",
594594
};
595595

596-
static const long samplerates400[] = {
596+
static const unsigned long long samplerates100[] = {
597+
DSL_HZ(10),
598+
DSL_HZ(20),
599+
DSL_HZ(50),
600+
DSL_HZ(100),
601+
DSL_HZ(200),
602+
DSL_HZ(500),
603+
DSL_KHZ(1),
604+
DSL_KHZ(2),
605+
DSL_KHZ(5),
606+
DSL_KHZ(10),
607+
DSL_KHZ(20),
608+
DSL_KHZ(40),
609+
DSL_KHZ(50),
610+
DSL_KHZ(100),
611+
DSL_KHZ(200),
612+
DSL_KHZ(400),
613+
DSL_KHZ(500),
614+
DSL_MHZ(1),
615+
DSL_MHZ(2),
616+
DSL_MHZ(4),
617+
DSL_MHZ(5),
618+
DSL_MHZ(10),
619+
DSL_MHZ(20),
620+
DSL_MHZ(25),
621+
DSL_MHZ(50),
622+
DSL_MHZ(100),
623+
0,
624+
};
625+
626+
static const unsigned long long samplerates400[] = {
597627
DSL_HZ(10),
598628
DSL_HZ(20),
599629
DSL_HZ(50),
@@ -625,7 +655,7 @@ static const long samplerates400[] = {
625655
0,
626656
};
627657

628-
static const long samplerates1000[] = {
658+
static const unsigned long long samplerates1000[] = {
629659
DSL_HZ(10),
630660
DSL_HZ(20),
631661
DSL_HZ(50),
@@ -784,6 +814,121 @@ static const dsl_vga vga_defaults[] = {
784814

785815
// supported devices
786816
static const dsl_profile dsl_profiles[] = {
817+
{
818+
0x2A0E,
819+
0x0020,
820+
LIBUSB_SPEED_HIGH,
821+
"DreamSourceLab",
822+
"DSLogic PLus",
823+
nullptr,
824+
"DSLogicPlus.fw",
825+
"DSLogicPlus.bin",
826+
"DSLogicPlus.bin",
827+
.dev_caps {
828+
.mode_caps = CAPS_MODE_LOGIC, // mode_caps
829+
.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF, // feature_caps
830+
.channels = DSL_CH(DSLogicDevice::DSL_STREAM20x16) |
831+
DSL_CH(DSLogicDevice::DSL_STREAM25x12) |
832+
DSL_CH(DSLogicDevice::DSL_STREAM50x6) |
833+
DSL_CH(DSLogicDevice::DSL_STREAM100x3) |
834+
DSL_CH(DSLogicDevice::DSL_BUFFER100x16) |
835+
DSL_CH(DSLogicDevice::DSL_BUFFER200x8) |
836+
DSL_CH(DSLogicDevice::DSL_BUFFER400x4), // channels
837+
.total_ch_num = 16, // total_ch_num
838+
.hw_depth = DSL_MB(256), // hw_depth
839+
.dso_depth = 0, // dso_depth
840+
.intest_channel = DSLogicDevice::DSL_BUFFER100x16, // intest_channel
841+
.vdivs = nullptr, // vdivs
842+
.samplerates = samplerates400, // samplerates
843+
.vga_id = 0x00, // vga_id
844+
.default_channelid = DSLogicDevice::DSL_STREAM50x6, // default_channelid
845+
.default_samplerate = DSL_MHZ(1), // default_samplerate
846+
.default_samplelimit = DSL_Mn(1), // default_samplelimit
847+
.default_pwmtrans = 0x0000, // default_pwmtrans
848+
.default_pwmmargin = 0x0000, // default_pwmmargin
849+
.ref_min = 0x00000000, // ref_min
850+
.ref_max = 0x00000000, // ref_max
851+
.default_comb_comp = 0x00, // default_comb_comp
852+
.half_samplerate = DSL_MHZ(200), // half_samplerate
853+
.quarter_samplerate = DSL_MHZ(400), // quarter_samplerate
854+
}
855+
},
856+
{
857+
0x2A0E,
858+
0x0021,
859+
LIBUSB_SPEED_HIGH,
860+
"DreamSourceLab",
861+
"DSLogic Basic",
862+
nullptr,
863+
"DSLogicBasic.fw",
864+
"DSLogicBasic.bin",
865+
"DSLogicBasic.bin",
866+
.dev_caps {
867+
.mode_caps = CAPS_MODE_LOGIC, // mode_caps
868+
.feature_caps = CAPS_FEATURE_VTH, // feature_caps
869+
.channels = DSL_CH(DSLogicDevice::DSL_STREAM20x16) |
870+
DSL_CH(DSLogicDevice::DSL_STREAM25x12) |
871+
DSL_CH(DSLogicDevice::DSL_STREAM50x6) |
872+
DSL_CH(DSLogicDevice::DSL_STREAM100x3) |
873+
DSL_CH(DSLogicDevice::DSL_BUFFER100x16) |
874+
DSL_CH(DSLogicDevice::DSL_BUFFER200x8) |
875+
DSL_CH(DSLogicDevice::DSL_BUFFER400x4), // channels
876+
.total_ch_num = 16, // total_ch_num
877+
.hw_depth = DSL_KB(256), // hw_depth
878+
.dso_depth = 0, // dso_depth
879+
.intest_channel = DSLogicDevice::DSL_STREAM20x16, // intest_channel
880+
.vdivs = nullptr, // vdivs
881+
.samplerates = samplerates400, // samplerates
882+
.vga_id = 0x00, // vga_id
883+
.default_channelid = DSLogicDevice::DSL_STREAM50x6, // default_channelid
884+
.default_samplerate = DSL_MHZ(1), // default_samplerate
885+
.default_samplelimit = DSL_Mn(1), // default_samplelimit
886+
.default_pwmtrans = 0x0000, // default_pwmtrans
887+
.default_pwmmargin = 0x0000, // default_pwmmargin
888+
.ref_min = 0x00000000, // ref_min
889+
.ref_max = 0x00000000, // ref_max
890+
.default_comb_comp = 0x00, // default_comb_comp
891+
.half_samplerate = DSL_MHZ(200), // half_samplerate
892+
.quarter_samplerate = DSL_MHZ(400), // quarter_samplerate
893+
}
894+
},
895+
{
896+
0x2A0E,
897+
0x0029,
898+
LIBUSB_SPEED_HIGH,
899+
"DreamSourceLab",
900+
"DSLogic U2Basic",
901+
nullptr,
902+
"DSLogicU2Basic.fw",
903+
"DSLogicU2Basic.bin",
904+
"DSLogicU2Basic.bin",
905+
.dev_caps {
906+
.mode_caps = CAPS_MODE_LOGIC, // mode_caps
907+
.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF, // feature_caps
908+
.channels = DSL_CH(DSLogicDevice::DSL_STREAM20x16) |
909+
DSL_CH(DSLogicDevice::DSL_STREAM25x12) |
910+
DSL_CH(DSLogicDevice::DSL_STREAM50x6) |
911+
DSL_CH(DSLogicDevice::DSL_STREAM100x3) |
912+
DSL_CH(DSLogicDevice::DSL_BUFFER100x16), // channels
913+
.total_ch_num = 16, // total_ch_num
914+
.hw_depth = DSL_MB(64), // hw_depth
915+
.dso_depth = 0, // dso_depth
916+
.intest_channel = DSLogicDevice::DSL_BUFFER100x16, // intest_channel
917+
.vdivs = nullptr, // vdivs
918+
.samplerates = samplerates100, // samplerates
919+
.vga_id = 0x00, // vga_id
920+
.default_channelid = DSLogicDevice::DSL_STREAM50x6, // default_channelid
921+
.default_samplerate = DSL_MHZ(1), // default_samplerate
922+
.default_samplelimit = DSL_Mn(1), // default_samplelimit
923+
.default_pwmtrans = 0x0000, // default_pwmtrans
924+
.default_pwmmargin = 0x0000, // default_pwmmargin
925+
.ref_min = 0x00000000, // ref_min
926+
.ref_max = 0x00000000, // ref_max
927+
.default_comb_comp = 0x00, // default_comb_comp
928+
.half_samplerate = DSL_MHZ(200), // half_samplerate
929+
.quarter_samplerate = DSL_MHZ(400), // quarter_samplerate
930+
}
931+
},
787932
{
788933
0x2A0E,
789934
0x002A,
@@ -822,45 +967,45 @@ static const dsl_profile dsl_profiles[] = {
822967
.quarter_samplerate = DSL_GHZ(1), // quarter_samplerate
823968
},
824969
},
825-
{
826-
0x2A0E,
827-
0x002A,
828-
LIBUSB_SPEED_SUPER,
829-
"DreamSourceLab",
830-
"DSLogic U3Pro16",
831-
nullptr,
832-
"DSLogicU3Pro16.fw",
833-
"DSLogicU3Pro16.bin",
834-
"DSLogicU3Pro16.bin",
835-
.dev_caps {
836-
.mode_caps = CAPS_MODE_LOGIC, // mode_caps
837-
.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_USB30 | CAPS_FEATURE_ADF4360, // feature_caps
838-
.channels = DSL_CH(DSLogicDevice::DSL_STREAM125x16_16) |
839-
DSL_CH(DSLogicDevice::DSL_STREAM250x12_16) |
840-
DSL_CH(DSLogicDevice::DSL_STREAM500x6) |
841-
DSL_CH(DSLogicDevice::DSL_STREAM1000x3) |
842-
DSL_CH(DSLogicDevice::DSL_BUFFER500x16) |
843-
DSL_CH(DSLogicDevice::DSL_BUFFER1000x8), // channels
844-
.total_ch_num = 16, // total_ch_num
845-
.hw_depth = DSL_GB(2), // hw_depth
846-
.dso_depth = 0, // dso_depth
847-
.intest_channel = DSLogicDevice::DSL_BUFFER500x16, // intest_channel
848-
.vdivs = nullptr, // vdivs
849-
.samplerates = samplerates1000, // samplerates
850-
.vga_id = 0x00, // vga_id
851-
.default_channelid = DSLogicDevice::DSL_STREAM500x6, // default_channelid
852-
.default_samplerate = DSL_MHZ(1), // default_samplerate
853-
.default_samplelimit = DSL_Mn(1), // default_samplelimit
854-
.default_pwmtrans = 0x0000, // default_pwmtrans
855-
.default_pwmmargin = 0x0000, // default_pwmmargin
856-
.ref_min = 0x00000000, // ref_min
857-
.ref_max = 0x00000000, // ref_max
858-
.default_comb_comp = 0x00, // default_comb_comp
859-
.half_samplerate = DSL_MHZ(500), // half_samplerate
860-
.quarter_samplerate = DSL_GHZ(1), // quarter_samplerate
970+
{
971+
0x2A0E,
972+
0x002A,
973+
LIBUSB_SPEED_SUPER,
974+
"DreamSourceLab",
975+
"DSLogic U3Pro16",
976+
nullptr,
977+
"DSLogicU3Pro16.fw",
978+
"DSLogicU3Pro16.bin",
979+
"DSLogicU3Pro16.bin",
980+
.dev_caps {
981+
.mode_caps = CAPS_MODE_LOGIC, // mode_caps
982+
.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_USB30 | CAPS_FEATURE_ADF4360, // feature_caps
983+
.channels = DSL_CH(DSLogicDevice::DSL_STREAM125x16_16) |
984+
DSL_CH(DSLogicDevice::DSL_STREAM250x12_16) |
985+
DSL_CH(DSLogicDevice::DSL_STREAM500x6) |
986+
DSL_CH(DSLogicDevice::DSL_STREAM1000x3) |
987+
DSL_CH(DSLogicDevice::DSL_BUFFER500x16) |
988+
DSL_CH(DSLogicDevice::DSL_BUFFER1000x8), // channels
989+
.total_ch_num = 16, // total_ch_num
990+
.hw_depth = DSL_GB(2), // hw_depth
991+
.dso_depth = 0, // dso_depth
992+
.intest_channel = DSLogicDevice::DSL_BUFFER500x16, // intest_channel
993+
.vdivs = nullptr, // vdivs
994+
.samplerates = samplerates1000, // samplerates
995+
.vga_id = 0x00, // vga_id
996+
.default_channelid = DSLogicDevice::DSL_STREAM500x6, // default_channelid
997+
.default_samplerate = DSL_MHZ(1), // default_samplerate
998+
.default_samplelimit = DSL_Mn(1), // default_samplelimit
999+
.default_pwmtrans = 0x0000, // default_pwmtrans
1000+
.default_pwmmargin = 0x0000, // default_pwmmargin
1001+
.ref_min = 0x00000000, // ref_min
1002+
.ref_max = 0x00000000, // ref_max
1003+
.default_comb_comp = 0x00, // default_comb_comp
1004+
.half_samplerate = DSL_MHZ(500), // half_samplerate
1005+
.quarter_samplerate = DSL_GHZ(1), // quarter_samplerate
1006+
},
8611007
},
862-
},
863-
{
1008+
{
8641009
0x2A0E,
8651010
0x002C,
8661011
LIBUSB_SPEED_HIGH,
@@ -900,47 +1045,85 @@ static const dsl_profile dsl_profiles[] = {
9001045
.quarter_samplerate = DSL_GHZ(1), // quarter_samplerate
9011046
},
9021047
},
903-
{
904-
0x2A0E,
905-
0x002C,
906-
LIBUSB_SPEED_SUPER,
907-
"DreamSourceLab",
908-
"DSLogic U3Pro32",
909-
nullptr,
910-
"DSLogicU3Pro32.fw",
911-
"DSLogicU3Pro32.bin",
912-
"DSLogicU3Pro32.bin",
913-
.dev_caps {
914-
.mode_caps = CAPS_MODE_LOGIC, // mode_caps
915-
.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_USB30 | CAPS_FEATURE_ADF4360 | CAPS_FEATURE_LA_CH32, // feature_caps
916-
.channels = DSL_CH(DSLogicDevice::DSL_STREAM50x32) |
917-
DSL_CH(DSLogicDevice::DSL_STREAM100x30) |
918-
DSL_CH(DSLogicDevice::DSL_STREAM250x12) |
919-
DSL_CH(DSLogicDevice::DSL_STREAM500x6) |
920-
DSL_CH(DSLogicDevice::DSL_STREAM1000x3) |
921-
DSL_CH(DSLogicDevice::DSL_BUFFER250x32) |
922-
DSL_CH(DSLogicDevice::DSL_BUFFER500x16) |
923-
DSL_CH(DSLogicDevice::DSL_BUFFER1000x8), // channels
924-
.total_ch_num = 32, // total_ch_num
925-
.hw_depth = DSL_GB(2), // hw_depth
926-
.dso_depth = 0, // dso_depth
927-
.intest_channel = DSLogicDevice::DSL_BUFFER250x32, // intest_channel
928-
.vdivs = nullptr, // vdivs
929-
.samplerates = samplerates1000, // samplerates
930-
.vga_id = 0x00, // vga_id
931-
.default_channelid = DSLogicDevice::DSL_STREAM500x6, // default_channelid
932-
.default_samplerate = DSL_MHZ(1), // default_samplerate
933-
.default_samplelimit = DSL_Mn(1), // default_samplelimit
934-
.default_pwmtrans = 0x0000, // default_pwmtrans
935-
.default_pwmmargin = 0x0000, // default_pwmmargin
936-
.ref_min = 0x00000000, // ref_min
937-
.ref_max = 0x00000000, // ref_max
938-
.default_comb_comp = 0x00, // default_comb_comp
939-
.half_samplerate = DSL_MHZ(500), // half_samplerate
940-
.quarter_samplerate = DSL_GHZ(1), // quarter_samplerate
1048+
{
1049+
0x2A0E,
1050+
0x002C,
1051+
LIBUSB_SPEED_SUPER,
1052+
"DreamSourceLab",
1053+
"DSLogic U3Pro32",
1054+
nullptr,
1055+
"DSLogicU3Pro32.fw",
1056+
"DSLogicU3Pro32.bin",
1057+
"DSLogicU3Pro32.bin",
1058+
.dev_caps {
1059+
.mode_caps = CAPS_MODE_LOGIC, // mode_caps
1060+
.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_USB30 | CAPS_FEATURE_ADF4360 | CAPS_FEATURE_LA_CH32, // feature_caps
1061+
.channels = DSL_CH(DSLogicDevice::DSL_STREAM50x32) |
1062+
DSL_CH(DSLogicDevice::DSL_STREAM100x30) |
1063+
DSL_CH(DSLogicDevice::DSL_STREAM250x12) |
1064+
DSL_CH(DSLogicDevice::DSL_STREAM500x6) |
1065+
DSL_CH(DSLogicDevice::DSL_STREAM1000x3) |
1066+
DSL_CH(DSLogicDevice::DSL_BUFFER250x32) |
1067+
DSL_CH(DSLogicDevice::DSL_BUFFER500x16) |
1068+
DSL_CH(DSLogicDevice::DSL_BUFFER1000x8), // channels
1069+
.total_ch_num = 32, // total_ch_num
1070+
.hw_depth = DSL_GB(2), // hw_depth
1071+
.dso_depth = 0, // dso_depth
1072+
.intest_channel = DSLogicDevice::DSL_BUFFER250x32, // intest_channel
1073+
.vdivs = nullptr, // vdivs
1074+
.samplerates = samplerates1000, // samplerates
1075+
.vga_id = 0x00, // vga_id
1076+
.default_channelid = DSLogicDevice::DSL_STREAM500x6, // default_channelid
1077+
.default_samplerate = DSL_MHZ(1), // default_samplerate
1078+
.default_samplelimit = DSL_Mn(1), // default_samplelimit
1079+
.default_pwmtrans = 0x0000, // default_pwmtrans
1080+
.default_pwmmargin = 0x0000, // default_pwmmargin
1081+
.ref_min = 0x00000000, // ref_min
1082+
.ref_max = 0x00000000, // ref_max
1083+
.default_comb_comp = 0x00, // default_comb_comp
1084+
.half_samplerate = DSL_MHZ(500), // half_samplerate
1085+
.quarter_samplerate = DSL_GHZ(1), // quarter_samplerate
1086+
},
9411087
},
942-
},
943-
{
1088+
{
1089+
0x2A0E,
1090+
0x002D,
1091+
LIBUSB_SPEED_HIGH,
1092+
"DreamSourceLab",
1093+
"DSLogic U2Pro16",
1094+
nullptr,
1095+
"DSLogicU2Pro16.fw",
1096+
"DSLogicU2Pro16.bin",
1097+
"DSLogicU2Pro16.bin",
1098+
.dev_caps {
1099+
.mode_caps = CAPS_MODE_LOGIC, // mode_caps
1100+
.feature_caps = CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_ADF4360 | CAPS_FEATURE_SECURITY, // feature_caps
1101+
.channels = DSL_CH(DSLogicDevice::DSL_STREAM20x16_3DN2) |
1102+
DSL_CH(DSLogicDevice::DSL_STREAM25x12_3DN2) |
1103+
DSL_CH(DSLogicDevice::DSL_STREAM50x6_3DN2) |
1104+
DSL_CH(DSLogicDevice::DSL_STREAM100x3_3DN2) |
1105+
DSL_CH(DSLogicDevice::DSL_BUFFER500x16) |
1106+
DSL_CH(DSLogicDevice::DSL_BUFFER1000x8), // channels
1107+
.total_ch_num = 16, // total_ch_num
1108+
.hw_depth = DSL_GB(4), // hw_depth
1109+
.dso_depth = 0, // dso_depth
1110+
.intest_channel = DSLogicDevice::DSL_BUFFER500x16, // intest_channel
1111+
.vdivs = nullptr, // vdivs
1112+
.samplerates = samplerates1000, // samplerates
1113+
.vga_id = 0x00, // vga_id
1114+
.default_channelid = DSLogicDevice::DSL_STREAM50x6_3DN2, // default_channelid
1115+
.default_samplerate = DSL_MHZ(1), // default_samplerate
1116+
.default_samplelimit = DSL_Mn(1), // default_samplelimit
1117+
.default_pwmtrans = 0x0000, // default_pwmtrans
1118+
.default_pwmmargin = 0x0000, // default_pwmmargin
1119+
.ref_min = 0x00000000, // ref_min
1120+
.ref_max = 0x00000000, // ref_max
1121+
.default_comb_comp = 0x00, // default_comb_comp
1122+
.half_samplerate = DSL_MHZ(500), // half_samplerate
1123+
.quarter_samplerate = DSL_GHZ(1), // quarter_samplerate
1124+
},
1125+
},
1126+
{
9441127
.vid = 0x2A0E,
9451128
.pid = 0x0030,
9461129
.usb_speed = LIBUSB_SPEED_HIGH,

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