DDR2 Controller Project

Objective and Overview

The goal of this project is to understand DRAM operations and improve substantial skills in hardware IP design. You'll use SystemVerilog to implement a DRAM controller IP for DDR2 (or its successors).

Your DDR2 controller will receive AXI requests and exercise a DDR2 model (Micron 512Mb DDR2).

DRAM Timing Parameters

SystemVerilog Interface