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[SYCL][FPGA] Remove support for intel::fpga_pipeline attribute (#6519)
Support for new FPGA attribute called [[intel::fpga_pipeline(N)]] on #6254 is no longer needed. This patch removes the support from frontend. Signed-off-by: Soumi Manna <soumi.manna@intel.com>
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‎clang/include/clang/Basic/Attr.td

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -2331,23 +2331,6 @@ def : MutualExclusions<[SYCLIntelFPGAIVDep,
23312331
def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency,
23322332
SYCLIntelFPGADisableLoopPipelining]>;
23332333

2334-
def SYCLIntelFPGAPipeline : InheritableAttr {
2335-
let Spellings = [CXX11<"intel","fpga_pipeline">];
2336-
let Args = [ExprArgument<"Value", /*optional*/1>];
2337-
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
2338-
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
2339-
ErrorDiag, "'for', 'while', and 'do' statements">;
2340-
let Documentation = [SYCLIntelFPGAPipelineAttrDocs];
2341-
let IsStmtDependent = 1;
2342-
}
2343-
2344-
def : MutualExclusions<[SYCLIntelFPGAInitiationInterval,
2345-
SYCLIntelFPGAPipeline]>;
2346-
def : MutualExclusions<[SYCLIntelFPGAIVDep,
2347-
SYCLIntelFPGAPipeline]>;
2348-
def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency,
2349-
SYCLIntelFPGAPipeline]>;
2350-
23512334
def SYCLIntelFPGALoopCount : StmtAttr {
23522335
let Spellings = [CXX11<"intel", "loop_count_min">,
23532336
CXX11<"intel", "loop_count_max">,
@@ -2380,9 +2363,6 @@ def SYCLIntelFPGAMaxInterleaving : StmtAttr {
23802363
def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining,
23812364
SYCLIntelFPGAMaxInterleaving]>;
23822365

2383-
def : MutualExclusions<[SYCLIntelFPGAPipeline,
2384-
SYCLIntelFPGAMaxInterleaving]>;
2385-
23862366
def SYCLIntelFPGASpeculatedIterations : StmtAttr {
23872367
let Spellings = [CXX11<"intel", "speculated_iterations">];
23882368
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
@@ -2395,9 +2375,6 @@ def SYCLIntelFPGASpeculatedIterations : StmtAttr {
23952375
def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining,
23962376
SYCLIntelFPGASpeculatedIterations]>;
23972377

2398-
def : MutualExclusions<[SYCLIntelFPGAPipeline,
2399-
SYCLIntelFPGASpeculatedIterations]>;
2400-
24012378
def SYCLIntelFPGANofusion : StmtAttr {
24022379
let Spellings = [CXX11<"intel","nofusion">];
24032380
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],

‎clang/include/clang/Basic/AttrDocs.td

Lines changed: 0 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -3328,58 +3328,6 @@ or ``ivdep``.
33283328
}];
33293329
}
33303330

3331-
def SYCLIntelFPGAPipelineAttrDocs : Documentation {
3332-
let Category = DocCatVariable;
3333-
let Heading = "intel::fpga_pipeline";
3334-
let Content = [{
3335-
The ``intel::fpga_pipeline(N)`` attribute applies to a loop and it allows users
3336-
to disable or enable pipelining iterations of a loop. The attribute optionally
3337-
accepts an integer constant expression that is converted to `bool`. A `true`
3338-
value enables pipelining while a `false` value disables pipelining. The
3339-
optional argument defaults to `true`. This attribute cannot be applied to a
3340-
loop in conjunction with the ``max_interleaving``, ``speculated_iterations``,
3341-
``max_concurrency``, ``initiation_interval``, or ``ivdep`` attributes.
3342-
3343-
.. code-block:: c++
3344-
3345-
// Disable loop pipelining
3346-
void bar() {
3347-
int a[10];
3348-
[[[intel::fpga_pipeline(0)]] for (int i = 0; i != 10; ++i) a[i] = 0;
3349-
}
3350-
3351-
// Enable loop pipelining
3352-
void foo() {
3353-
int var = 0;
3354-
[[intel::fpga_pipeline(1)]] for (int i = 0; i < 10; ++i) var++;
3355-
}
3356-
3357-
void Array(int *array, size_t n) {
3358-
// identical to [[intel::fpga_pipeline(1)]]
3359-
[[intel::fpga_pipeline]] for (int i = 0; i < n; ++i) array[i] = 0;
3360-
}
3361-
3362-
void count () {
3363-
int a1[10], int i = 0;
3364-
[[intel::fpga_pipeline(1)]] while (i < 10) {
3365-
a1[i] += 3;
3366-
}
3367-
3368-
void check() {
3369-
int a = 10;
3370-
[[intel::fpga_pipeline(1)]] do {
3371-
a = a + 1;
3372-
} while (a < 20);
3373-
}
3374-
3375-
template<int A>
3376-
void func() {
3377-
[[intel::fpga_pipeline(A)]] for(;;) { }
3378-
}
3379-
3380-
}];
3381-
}
3382-
33833331
def SYCLIntelFPGALoopCountAttrDocs : Documentation {
33843332
let Category = DocCatVariable;
33853333
let Heading = "intel::loop_count_min, intel::loop_count_max, intel::loop_count_avg, intel::loop_count";

‎clang/include/clang/Sema/Sema.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2288,9 +2288,6 @@ class Sema final {
22882288
SYCLIntelFPGALoopCoalesceAttr *
22892289
BuildSYCLIntelFPGALoopCoalesceAttr(const AttributeCommonInfo &CI, Expr *E);
22902290

2291-
SYCLIntelFPGAPipelineAttr *
2292-
BuildSYCLIntelFPGAPipelineAttr(const AttributeCommonInfo &CI, Expr *E);
2293-
22942291
bool CheckQualifiedFunctionForTypeId(QualType T, SourceLocation Loc);
22952292

22962293
bool CheckFunctionReturnType(QualType T, SourceLocation Loc);

‎clang/lib/CodeGen/CGLoopInfo.cpp

Lines changed: 1 addition & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -612,13 +612,6 @@ MDNode *LoopInfo::createMetadata(
612612
LoopProperties.push_back(MDNode::get(Ctx, Vals));
613613
}
614614

615-
for (auto &FP : Attrs.SYCLIntelFPGAPipeline) {
616-
Metadata *Vals[] = {MDString::get(Ctx, FP.first),
617-
ConstantAsMetadata::get(ConstantInt::get(
618-
llvm::Type::getInt32Ty(Ctx), FP.second))};
619-
LoopProperties.push_back(MDNode::get(Ctx, Vals));
620-
}
621-
622615
LoopProperties.insert(LoopProperties.end(), AdditionalLoopProperties.begin(),
623616
AdditionalLoopProperties.end());
624617
return createFullUnrollMetadata(Attrs, LoopProperties, HasUserTransforms);
@@ -662,7 +655,6 @@ void LoopAttributes::clear() {
662655
PipelineDisabled = false;
663656
PipelineInitiationInterval = 0;
664657
SYCLNofusionEnable = false;
665-
SYCLIntelFPGAPipeline.clear();
666658
MustProgress = false;
667659
}
668660

@@ -696,8 +688,7 @@ LoopInfo::LoopInfo(BasicBlock *Header, const LoopAttributes &Attrs,
696688
Attrs.UnrollEnable == LoopAttributes::Unspecified &&
697689
Attrs.UnrollAndJamEnable == LoopAttributes::Unspecified &&
698690
Attrs.DistributeEnable == LoopAttributes::Unspecified && !StartLoc &&
699-
Attrs.SYCLNofusionEnable == false &&
700-
Attrs.SYCLIntelFPGAPipeline.empty() && !EndLoc && !Attrs.MustProgress)
691+
Attrs.SYCLNofusionEnable == false && !EndLoc && !Attrs.MustProgress)
701692
return;
702693

703694
TempLoopID = MDNode::getTemporary(Header->getContext(), None);
@@ -1021,8 +1012,6 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx,
10211012
// emitted
10221013
// For attribute nofusion:
10231014
// 'llvm.loop.fusion.disable' metadata will be emitted
1024-
// For attribute fpga_pipeline:
1025-
// n - 'llvm.loop.intel.pipelining.enable, i32 n' metadata will be emitted
10261015
for (const auto *A : Attrs) {
10271016
if (const auto *IntelFPGAIVDep = dyn_cast<SYCLIntelFPGAIVDepAttr>(A))
10281017
addSYCLIVDepInfo(Header->getContext(), IntelFPGAIVDep->getSafelenValue(),
@@ -1087,15 +1076,6 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx,
10871076

10881077
if (isa<SYCLIntelFPGANofusionAttr>(A))
10891078
setSYCLNofusionEnable();
1090-
1091-
if (const auto *IntelFPGAPipeline =
1092-
dyn_cast<SYCLIntelFPGAPipelineAttr>(A)) {
1093-
const auto *CE = cast<ConstantExpr>(IntelFPGAPipeline->getValue());
1094-
Optional<llvm::APSInt> ArgVal = CE->getResultAsAPSInt();
1095-
unsigned int Value = ArgVal->getBoolValue() ? 1 : 0;
1096-
const char *Var = "llvm.loop.intel.pipelining.enable";
1097-
setSYCLIntelFPGAPipeline(Var, Value);
1098-
}
10991079
}
11001080

11011081
setMustProgress(MustProgress);

‎clang/lib/CodeGen/CGLoopInfo.h

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -152,10 +152,6 @@ struct LoopAttributes {
152152
/// Flag for llvm.loop.fusion.disable metatdata.
153153
bool SYCLNofusionEnable;
154154

155-
/// Value for fpga_pipeline variant and metadata.
156-
llvm::SmallVector<std::pair<const char *, unsigned int>, 2>
157-
SYCLIntelFPGAPipeline;
158-
159155
/// Value for whether the loop is required to make progress.
160156
bool MustProgress;
161157
};
@@ -411,11 +407,6 @@ class LoopInfoStack {
411407
/// Set flag of nofusion for the next loop pushed.
412408
void setSYCLNofusionEnable() { StagedAttrs.SYCLNofusionEnable = true; }
413409

414-
/// Set variant and value of fpga_pipeline for the next loop pushed.
415-
void setSYCLIntelFPGAPipeline(const char *Var, unsigned int Value) {
416-
StagedAttrs.SYCLIntelFPGAPipeline.push_back({Var, Value});
417-
}
418-
419410
/// Set no progress for the next loop pushed.
420411
void setMustProgress(bool P) { StagedAttrs.MustProgress = P; }
421412

‎clang/lib/Sema/SemaStmtAttr.cpp

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -219,33 +219,6 @@ static Attr *handleSYCLIntelFPGADisableLoopPipeliningAttr(Sema &S, Stmt *,
219219
return new (S.Context) SYCLIntelFPGADisableLoopPipeliningAttr(S.Context, A);
220220
}
221221

222-
// Handle [[intel:fpga_pipeline]] attribute.
223-
static Attr *handleSYCLIntelFPGAPipelineAttr(Sema &S, Stmt *,
224-
const ParsedAttr &A) {
225-
// If no attribute argument is specified, set to default value '1'.
226-
Expr *E = A.isArgExpr(0)
227-
? A.getArgAsExpr(0)
228-
: IntegerLiteral::Create(S.Context, llvm::APInt(32, 1),
229-
S.Context.IntTy, A.getLoc());
230-
231-
return S.BuildSYCLIntelFPGAPipelineAttr(A, E);
232-
}
233-
234-
SYCLIntelFPGAPipelineAttr *
235-
Sema::BuildSYCLIntelFPGAPipelineAttr(const AttributeCommonInfo &A, Expr *E) {
236-
237-
if (!E->isValueDependent()) {
238-
// Check if the expression is not value dependent.
239-
llvm::APSInt ArgVal;
240-
ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal);
241-
if (Res.isInvalid())
242-
return nullptr;
243-
E = Res.get();
244-
}
245-
246-
return new (Context) SYCLIntelFPGAPipelineAttr(Context, A, E);
247-
}
248-
249222
static bool checkSYCLIntelFPGAIVDepSafeLen(Sema &S, llvm::APSInt &Value,
250223
Expr *E) {
251224
// This attribute requires a non-negative value.
@@ -855,7 +828,6 @@ static void CheckForIncompatibleSYCLLoopAttributes(
855828
CheckForDuplicationSYCLLoopAttribute<LoopUnrollHintAttr>(S, Attrs, false);
856829
CheckRedundantSYCLIntelFPGAIVDepAttrs(S, Attrs);
857830
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGANofusionAttr>(S, Attrs);
858-
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAPipelineAttr>(S, Attrs);
859831
}
860832

861833
void CheckForIncompatibleUnrollHintAttributes(
@@ -1001,8 +973,6 @@ static Attr *ProcessStmtAttribute(Sema &S, Stmt *St, const ParsedAttr &A,
1001973
return handleUnlikely(S, St, A, Range);
1002974
case ParsedAttr::AT_SYCLIntelFPGANofusion:
1003975
return handleIntelFPGANofusionAttr(S, St, A);
1004-
case ParsedAttr::AT_SYCLIntelFPGAPipeline:
1005-
return handleSYCLIntelFPGAPipelineAttr(S, St, A);
1006976
default:
1007977
// N.B., ClangAttrEmitter.cpp emits a diagnostic helper that ensures a
1008978
// declaration attribute is not written on a statement, but this code is

‎clang/lib/Sema/SemaTemplateInstantiate.cpp

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1112,8 +1112,6 @@ namespace {
11121112
const SYCLIntelFPGASpeculatedIterationsAttr *SI);
11131113
const SYCLIntelFPGALoopCountAttr *
11141114
TransformSYCLIntelFPGALoopCountAttr(const SYCLIntelFPGALoopCountAttr *SI);
1115-
const SYCLIntelFPGAPipelineAttr *
1116-
TransformSYCLIntelFPGAPipelineAttr(const SYCLIntelFPGAPipelineAttr *SI);
11171115

11181116
ExprResult TransformPredefinedExpr(PredefinedExpr *E);
11191117
ExprResult TransformDeclRefExpr(DeclRefExpr *E);
@@ -1605,13 +1603,6 @@ const LoopUnrollHintAttr *TemplateInstantiator::TransformLoopUnrollHintAttr(
16051603
return getSema().BuildLoopUnrollHintAttr(*LU, TransformedExpr);
16061604
}
16071605

1608-
const SYCLIntelFPGAPipelineAttr *
1609-
TemplateInstantiator::TransformSYCLIntelFPGAPipelineAttr(
1610-
const SYCLIntelFPGAPipelineAttr *PA) {
1611-
Expr *TransformedExpr = getDerived().TransformExpr(PA->getValue()).get();
1612-
return getSema().BuildSYCLIntelFPGAPipelineAttr(*PA, TransformedExpr);
1613-
}
1614-
16151606
ExprResult TemplateInstantiator::transformNonTypeTemplateParmRef(
16161607
NonTypeTemplateParmDecl *parm,
16171608
SourceLocation loc,

‎clang/test/CodeGenSYCL/intel-fpga-loops.cpp

Lines changed: 1 addition & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -20,14 +20,6 @@
2020
// CHECK: br label %for.cond2, !llvm.loop ![[MD_LCA_1:[0-9]+]]
2121
// CHECK: br label %for.cond13, !llvm.loop ![[MD_LCA_2:[0-9]+]]
2222
// CHECK: br label %for.cond24, !llvm.loop ![[MD_LCA_3:[0-9]+]]
23-
// CHECK: br label %for.cond, !llvm.loop ![[MD_FP:[0-9]+]]
24-
// CHECK: br label %for.cond2, !llvm.loop ![[MD_FP_1:[0-9]+]]
25-
// CHECK: br label %for.cond13, !llvm.loop ![[MD_FP_2:[0-9]+]]
26-
// CHECK: br label %for.cond24, !llvm.loop ![[MD_FP_3:[0-9]+]]
27-
// CHECK: br label %while.cond, !llvm.loop ![[MD_FP_4:[0-9]+]]
28-
// CHECK: br i1 %cmp38, label %do.body, label %do.end, !llvm.loop ![[MD_FP_5:[0-9]+]]
29-
// CHECK: br label %for.cond40, !llvm.loop ![[MD_FP_6:[0-9]+]]
30-
// CHECK: br label %while.cond47, !llvm.loop ![[MD_FP_7:[0-9]+]]
3123

3224
void disable_loop_pipelining() {
3325
int a[10];
@@ -134,7 +126,7 @@ void speculated_iterations() {
134126
a[i] = 0;
135127
}
136128

137-
// Add CodeGen tests for FPGA loop attribute: [[intel::fpga_pipeline()]].
129+
// Add CodeGen tests for FPGA loop_count attributes.
138130
template <int A>
139131
void loop_count_control() {
140132
int a[10];
@@ -159,48 +151,6 @@ void loop_count_control() {
159151
a[i] = 0;
160152
}
161153

162-
// Add CodeGen tests for Loop attribute: [[intel::fpga_pipeline()]].
163-
template <int A>
164-
void fpga_pipeline() {
165-
int a[10];
166-
// CHECK: ![[MD_FP]] = distinct !{![[MD_FP]], ![[MP]], ![[MD_fpga_pipeline:[0-9]+]]}
167-
// CHECK-NEXT: ![[MD_fpga_pipeline]] = !{!"llvm.loop.intel.pipelining.enable", i32 1}
168-
[[intel::fpga_pipeline(A)]] for (int i = 0; i != 10; ++i)
169-
a[i] = 0;
170-
171-
// CHECK: ![[MD_FP_1]] = distinct !{![[MD_FP_1]], ![[MP]], ![[MD_fpga_pipeline]]}
172-
[[intel::fpga_pipeline(1)]] for (int i = 0; i != 10; ++i)
173-
a[i] = 0;
174-
175-
// CHECK: ![[MD_FP_2]] = distinct !{![[MD_FP_2]], ![[MP]], ![[MD_fpga_pipeline]]}
176-
[[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i)
177-
a[i] = 0;
178-
179-
// CHECK: ![[MD_FP_3]] = distinct !{![[MD_FP_3]], ![[MP]], ![[MD_dlp]]}
180-
[[intel::fpga_pipeline(0)]] for (int i = 0; i != 10; ++i)
181-
a[i] = 0;
182-
183-
// CHECK: ![[MD_FP_4]] = distinct !{![[MD_FP_4]], ![[MP]], ![[MD_fpga_pipeline]]}
184-
int j = 0;
185-
[[intel::fpga_pipeline]] while (j < 10) {
186-
a[j] += 3;
187-
}
188-
189-
// CHECK: ![[MD_FP_5]] = distinct !{![[MD_FP_5]], ![[MP]], ![[MD_fpga_pipeline]]}
190-
int b = 10;
191-
[[intel::fpga_pipeline(1)]] do {
192-
b = b + 1;
193-
} while (b < 20);
194-
195-
// CHECK: ![[MD_FP_6]] = distinct !{![[MD_FP_6]], ![[MD_fpga_pipeline]]}
196-
int c[] = {0, 1, 2, 3, 4, 5};
197-
[[intel::fpga_pipeline(A)]] for (int n : c) { n *= 2; }
198-
199-
// CHECK: ![[MD_FP_7]] = distinct !{![[MD_FP_7]], ![[MP]], ![[MD_fpga_pipeline]]}
200-
int k = 0;
201-
[[intel::fpga_pipeline(-1)]] while (k < 20) { a[k] += 2; }
202-
}
203-
204154
template <typename name, typename Func>
205155
__attribute__((sycl_kernel)) void kernel_single_task(const Func &kernelFunc) {
206156
kernelFunc();
@@ -216,7 +166,6 @@ int main() {
216166
max_interleaving<3, 0>();
217167
speculated_iterations<4, 0>();
218168
loop_count_control<12>();
219-
fpga_pipeline<1>();
220169
});
221170
return 0;
222171
}

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