Merge from 'sycl' to 'sycl-web'

Author: iclsrc

clang/include/clang/Basic/AttrDocs.td

@@ -417,11 +417,11 @@ The types that own this attribute are excluded from device-copyable and other
 type-legalization steps.
 
 .. code-block:: c++
-  class __attribute__((sycl_special_class)) accessor {
 
-private:
-  void __init() {}
-};
+  class __attribute__((sycl_special_class)) accessor {
+    private:
+      void __init() {}
+  };
   }];
 }
 

libclc/ptx-nvidiacl/libspirv/integer/mul_hi.cl

@@ -30,7 +30,8 @@ _CLC_OVERLOAD _CLC_DEF ulong __spirv_ocl_u_mul_hi(ulong x, ulong y) {
 
 #define __CLC_MUL_HI_IMPL(BGENTYPE, SPV_MUL_HI, GENTYPE, GENSIZE)              \
   _CLC_OVERLOAD _CLC_DEF GENTYPE SPV_MUL_HI(GENTYPE x, GENTYPE y) {            \
-    return (GENTYPE)(SPV_MUL_HI((BGENTYPE)x, (BGENTYPE)y) >> GENSIZE);         \
+    return (GENTYPE)SPV_MUL_HI((BGENTYPE)(((BGENTYPE)x) << GENSIZE),           \
+                               (BGENTYPE)y);                                   \
   }
 
 __CLC_MUL_HI_IMPL(short, __spirv_ocl_s_mul_hi, char, 8)

llvm/test/tools/sycl-post-link/spec-constants/SYCL-2020.ll

@@ -27,6 +27,8 @@
 %class.specialization_id.6 = type { %struct.MArrayConst3 }
 %struct.MArrayConst4 = type { [2 x [2 x [3 x i32]]] }
 %class.specialization_id.7 = type { %struct.MArrayConst4 }
+%class.specialization_id.8 = type { %struct.ComposConst3 }
+%struct.ComposConst3 = type { i32, i32, %struct.myConst}
 
 @id_half = dso_local global %class.specialization_id { half 0xH4000 }, align 8
 @id_int = dso_local global %class.specialization_id.0 { i32 42 }, align 4
@@ -37,6 +39,7 @@
 @id_marray2 = dso_local global %class.specialization_id.5 { %struct.MArrayConst2 { [3 x i32] [i32 1, i32 2, i32 3]  } }, align 8
 @id_marray3 = dso_local global %class.specialization_id.6 { %struct.MArrayConst3 { [3 x i64] [i64 1, i64 2, i64 3]  } }, align 8
 @id_marray4 = dso_local global %class.specialization_id.7 { %struct.MArrayConst4 { [2 x [2 x [3 x i32]]] [[2 x [3 x i32]] [[3 x i32] [i32 1, i32 2, i32 3], [3 x i32] [i32 1, i32 2, i32 3]], [2 x [3 x i32]] [[3 x i32] [i32 1, i32 2, i32 3], [3 x i32] [i32 1, i32 2, i32 3]]]  } }, align 8
+@id_compos3 = dso_local global %class.specialization_id.8 zeroinitializer, align 4
 
 ; check that the following globals are preserved: even though they are won't be
 ; used in the module anymore, they could still be referenced by debug info
@@ -51,6 +54,7 @@
 @__builtin_unique_stable_name._Z27get_specialization_constantIL_Z6id_intE17specialization_idIiEiET1_v = private unnamed_addr constant [34 x i8] c"_ZTS14name_generatorIL_Z6id_intEE\00", align 1
 @__builtin_unique_stable_name._Z27get_specialization_constantIL_Z9id_composE17specialization_idI11ComposConstES1_ET1_v = private unnamed_addr constant [37 x i8] c"_ZTS14name_generatorIL_Z9id_composEE\00", align 1
 @__builtin_unique_stable_name._Z27get_specialization_constantIL_Z10id_compos2E17specialization_idI12ComposConst2ES1_ET1_v = private unnamed_addr constant [39 x i8] c"_ZTS14name_generatorIL_Z10id_compos2EE\00", align 1
+@__builtin_unique_stable_name._Z27get_specialization_constantIL_Z10id_compos3E17specialization_idI12ComposConst3ES1_ET1_v = private unnamed_addr constant [39 x i8] c"_ZTS14name_generatorIL_Z10id_compos3EE\00", align 1
 @__builtin_unique_stable_name._Z27get_specialization_constantIL_Z10id_vectorE17specialization_idI11VectorConstES1_ET1_v = private unnamed_addr constant [38 x i8] c"_ZTS14name_generatorIL_Z10id_vectorEE\00", align 1
 @__builtin_unique_stable_name._Z27get_specialization_constantIL_Z10id_marrayE17specialization_idI11MArrayConstES1_ET1_v = private unnamed_addr constant [38 x i8] c"_ZTS14name_generatorIL_Z10id_marrayEE\00", align 1
 @__builtin_unique_stable_name.id_marray2 = private unnamed_addr constant [39 x i8] c"_ZTS14name_generatorIL_Z10id_marray2EE\00", align 1
@@ -141,29 +145,46 @@ entry:
   ret void
 }
 
+define void @test_zeroinit() {
+  %tmp = alloca %struct.ComposConst3, align 4
+  %1 = bitcast %struct.ComposConst3* %tmp to i8*
+; CHECK-DEF: %[[GEP3:[0-9a-z]+]] = getelementptr i8, i8* null, i32 54
+; CHECK-DEF: %[[BITCAST3:[0-9a-z]+]] = bitcast i8* %[[GEP3]] to %struct.ComposConst3*
+; CHECK-DEF: %[[C3:[0-9a-z]+]] = load %struct.ComposConst3, %struct.ComposConst3* %[[BITCAST3]], align 4
+;
+; CHECK-RT: %[[#SE5:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID10:]], i32 0)
+; CHECK-RT: %[[#SE6:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID11:]], i32 0)
+; CHECK-RT: %[[#SE7:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID12:]], i32 0)
+; CHECK-RT: %[[#SE8:]] = call float @_Z20__spirv_SpecConstantif(i32 [[#SCID13:]], float 0.000000e+00)
+; CHECK-RT: %[[#SE9:]] = call %struct.myConst @_Z29__spirv_SpecConstantCompositeif_Rstruct.myConst(i32 %[[#SE7]], float %[[#SE8]])
+; CHECK-RT: call %struct.ComposConst3 @_Z29__spirv_SpecConstantCompositeiistruct.myConst_Rstruct.ComposConst3(i32 %[[#SE5]], i32 %[[#SE6]], %struct.myConst %[[#SE9]])
+  call void @_Z40__sycl_getComposite2020SpecConstantValueI12ComposConst3ET_PKcPvS4_(%struct.ComposConst3* sret(%struct.ComposConst3) align 4 %tmp, i8* getelementptr inbounds ([39 x i8], [39 x i8]* @__builtin_unique_stable_name._Z27get_specialization_constantIL_Z10id_compos3E17specialization_idI12ComposConst3ES1_ET1_v, i64 0, i64 0), i8* bitcast (%class.specialization_id.8* @id_compos3 to i8*), i8* null)
+  ret void
+}
+
 define void @test3() {
   %tmp = alloca %struct.VectorConst, align 8
   %tmp1 = alloca %struct.MArrayConst, align 8
   %tmp2 = alloca %struct.MArrayConst2, align 8
   %tmp3 = alloca %struct.MArrayConst3, align 8
   %tmp4 = alloca %struct.MArrayConst4, align 8
   %1 = bitcast %struct.VectorConst* %tmp to i8*
-; CHECK-DEF: %[[GEP1:[0-9a-z]+]] = getelementptr i8, i8* null, i32 54
+; CHECK-DEF: %[[GEP1:[0-9a-z]+]] = getelementptr i8, i8* null, i32 70
 ; CHECK-DEF: %[[BITCAST1:[0-9a-z]+]] = bitcast i8* %[[GEP1]] to %struct.VectorConst*
 ; CHECK-DEF: %[[C1:[0-9a-z]+]] = load %struct.VectorConst, %struct.VectorConst* %[[BITCAST1]], align 8
 ;
-; CHECK-RT: %[[#SE1:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID10:]], i32 1)
-; CHECK-RT: %[[#SE2:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID11:]], i32 2)
+; CHECK-RT: %[[#SE1:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID14:]], i32 1)
+; CHECK-RT: %[[#SE2:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID15:]], i32 2)
 ; CHECK-RT: %[[#CE1:]] = call <2 x i32> @_Z29__spirv_SpecConstantCompositeii_RDv2_i(i32 %[[#SE1]], i32 %[[#SE2]])
 ; CHECK-RT: call %struct.VectorConst @_Z29__spirv_SpecConstantCompositeDv2_i_Rstruct.VectorConst(<2 x i32> %[[#CE1]])
   call void @_Z40__sycl_getComposite2020SpecConstantValueI11VectorConstET_PKcPvS4_(%struct.VectorConst* nonnull sret(%struct.VectorConst) align 8 %tmp, i8* getelementptr inbounds ([38 x i8], [38 x i8]* @__builtin_unique_stable_name._Z27get_specialization_constantIL_Z10id_vectorE17specialization_idI11VectorConstES1_ET1_v, i64 0, i64 0), i8* bitcast (%class.specialization_id.3* @id_vector to i8*), i8* null)
   %2 = bitcast %struct.MArrayConst* %tmp1 to i8*
-; CHECK-DEF: %[[GEP2:[0-9a-z]+]] = getelementptr i8, i8* null, i32 62
+; CHECK-DEF: %[[GEP2:[0-9a-z]+]] = getelementptr i8, i8* null, i32 78
 ; CHECK-DEF: %[[BITCAST2:[0-9a-z]+]] = bitcast i8* %[[GEP2]] to %struct.MArrayConst*
 ; CHECK-DEF: %[[C2:[0-9a-z]+]] = load %struct.MArrayConst, %struct.MArrayConst* %[[BITCAST2]], align 4
 ;
-; CHECK-RT: %[[#SE1:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID12:]], i32 1)
-; CHECK-RT: %[[#SE2:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID13:]], i32 2)
+; CHECK-RT: %[[#SE1:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID16:]], i32 1)
+; CHECK-RT: %[[#SE2:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID17:]], i32 2)
 ; CHECK-RT: %[[#CE1:]] = call [2 x i32] @_Z29__spirv_SpecConstantCompositeii_RA2_i(i32 %[[#SE1]], i32 %[[#SE2]])
 ; CHECK-RT: call %struct.MArrayConst @_Z29__spirv_SpecConstantCompositeA2_i_Rstruct.MArrayConst([2 x i32] %[[#CE1]])
   call void @_Z40__sycl_getComposite2020SpecConstantValueI11MArrayConstET_PKcPvS4_(%struct.MArrayConst* nonnull sret(%struct.MArrayConst) align 8 %tmp1, i8* getelementptr inbounds ([38 x i8], [38 x i8]* @__builtin_unique_stable_name._Z27get_specialization_constantIL_Z10id_marrayE17specialization_idI11MArrayConstES1_ET1_v, i64 0, i64 0), i8* bitcast (%class.specialization_id.4* @id_marray to i8*), i8* null)
@@ -194,6 +215,8 @@ declare dso_local void @_Z40__sycl_getComposite2020SpecConstantValueI11ComposCon
 
 declare dso_local void @_Z40__sycl_getComposite2020SpecConstantValueI12ComposConst2ET_PKcPvS4_(%struct.ComposConst2* sret(%struct.ComposConst2) align 8, i8*, i8*, i8*) local_unnamed_addr #2
 
+declare dso_local void @_Z40__sycl_getComposite2020SpecConstantValueI12ComposConst3ET_PKcPvS4_(%struct.ComposConst3* sret(%struct.ComposConst3) align 8, i8*, i8*, i8*) local_unnamed_addr #2
+
 declare dso_local void @_Z40__sycl_getComposite2020SpecConstantValueI11VectorConstET_PKcPvS4_(%struct.VectorConst* sret(%struct.VectorConst) align 8, i8*, i8*, i8*) local_unnamed_addr #2
 
 declare dso_local void @_Z40__sycl_getComposite2020SpecConstantValueI11MArrayConstET_PKcPvS4_(%struct.MArrayConst* sret(%struct.MArrayConst) align 8, i8*, i8*, i8*) local_unnamed_addr #2
@@ -209,9 +232,9 @@ attributes #1 = { argmemonly nofree nosync nounwind willreturn }
 attributes #2 = { "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="true" "use-soft-float"="false" }
 attributes #3 = { nounwind }
 
-; CHECK: !sycl.specialization-constants = !{![[#ID0:]], ![[#ID1:]], ![[#ID2:]], ![[#ID3:]], ![[#ID4:]], ![[#ID5:]]
+; CHECK: !sycl.specialization-constants = !{![[#ID0:]], ![[#ID1:]], ![[#ID2:]], ![[#ID3:]], ![[#ID_COMPOS3:]], ![[#ID4:]], ![[#ID5:]]
 ;
-; CHECK-DEF: !sycl.specialization-constants-default-values = !{![[#ID4:]], ![[#ID5:]], ![[#ID6:]], ![[#ID7:]], ![[#ID8:]], ![[#ID9:]]
+; CHECK-DEF: !sycl.specialization-constants-default-values = !{![[#ID4:]], ![[#ID5:]], ![[#ID6:]], ![[#ID7:]], ![[#ID_COMPOS3_DEFAULT:]], ![[#ID8:]], ![[#ID9:]]
 ; CHECK-RT-NOT: !sycl.specialization-constants-default-values
 ;
 ; CHECK: ![[#ID0]] = !{!"_ZTS14name_generatorIL_Z9id_halfEE", i32 0, i32 0, i32 2}
@@ -221,6 +244,7 @@ attributes #3 = { nounwind }
 ;
 ; CHECK-DEF: ![[#ID2]] = !{!"_ZTS14name_generatorIL_Z9id_composEE", i32 2, i32 0, i32 24}
 ; CHECK-DEF: ![[#ID3]] = !{!"_ZTS14name_generatorIL_Z10id_compos2EE", i32 3, i32 0, i32 24
+; CHECK-DEF: ![[#ID_COMPOS3]] = !{!"_ZTS14name_generatorIL_Z10id_compos3EE", i32 4, i32 0, i32 16
 ;
 ; CHECK-RT: ![[#ID2]] = !{!"_ZTS14name_generatorIL_Z9id_composEE", i32 [[#SCID2]], i32 0, i32 4,
 ; CHECK-RT-SAME: i32 [[#SCID3]], i32 8, i32 8,
@@ -235,14 +259,15 @@ attributes #3 = { nounwind }
 ; CHECK-DEF: ![[#ID5]] = !{i32 42}
 ; CHECK-DEF: ![[#ID6]] = !{%struct.ComposConst { i32 1, double 2.000000e+00, %struct.myConst { i32 13, float 0x4020666660000000 } }}
 ; CHECK-DEF: ![[#ID7]] = !{%struct.ComposConst2 { i8 1, %struct.myConst { i32 52, float 0x40479999A0000000 }, double 2.000000e+00 }}
+; CHECK-DEF: ![[#ID_COMPOS3_DEFAULT]] = !{%struct.ComposConst3 zeroinitializer}
 ;
 ; CHECK-DEF: ![[#ID8]] = !{%struct.VectorConst { <2 x i32> <i32 1, i32 2> }}
 ; CHECK-DEF: ![[#ID9]] = !{%struct.MArrayConst { [2 x i32] [i32 1, i32 2] }}
 ;
-; CHECK-RT: ![[#ID4]] = !{!"_ZTS14name_generatorIL_Z10id_vectorEE", i32 [[#SCID10]], i32 0, i32 4,
-; CHECK-RT-SAME: i32 [[#SCID11]], i32 4, i32 4}
-; CHECK-RT: ![[#ID5]] = !{!"_ZTS14name_generatorIL_Z10id_marrayEE", i32 [[#SCID12]], i32 0, i32 4,
-; CHECK-RT-SAME: i32 [[#SCID13]], i32 4, i32 4}
+; CHECK-RT: ![[#ID4]] = !{!"_ZTS14name_generatorIL_Z10id_vectorEE", i32 [[#SCID14]], i32 0, i32 4,
+; CHECK-RT-SAME: i32 [[#SCID15]], i32 4, i32 4}
+; CHECK-RT: ![[#ID5]] = !{!"_ZTS14name_generatorIL_Z10id_marrayEE", i32 [[#SCID16]], i32 0, i32 4,
+; CHECK-RT-SAME: i32 [[#SCID17]], i32 4, i32 4}
 
 ; CHECK-PROPS: [SYCL/specialization constants]
 ; CHECK-PROPS: _ZTS14name_generatorIL_Z9id_halfEE=2|

llvm/tools/sycl-post-link/SpecConstants.cpp

@@ -314,7 +314,11 @@ void collectCompositeElementsDefaultValuesRecursive(
   } else if (auto *StructTy = dyn_cast<StructType>(Ty)) {
     const StructLayout *SL = M.getDataLayout().getStructLayout(StructTy);
     for (size_t I = 0, E = StructTy->getNumElements(); I < E; ++I) {
-      Constant *El = cast<Constant>(C->getOperand(I));
+      Constant *El = nullptr;
+      if (C->isZeroValue())
+        El = Constant::getNullValue(StructTy->getElementType(I));
+      else
+        El = cast<Constant>(C->getOperand(I));
       // When handling elements of a structure, we do not use manually
       // calculated offsets (which are sum of sizes of all previously
       // encountered elements), but instead rely on data provided for us by

sycl/doc/CompilerAndRuntimeDesign.md

@@ -538,8 +538,12 @@ passed to `-fsycl-targets`.
 Unlike other AOT targets, the bitcode module linked from intermediate compiled
 objects never goes through SPIR-V. Instead it is passed directly in bitcode form
 down to the NVPTX Back End. All produced bitcode depends on two libraries,
-`libdevice.bc` (provided by the CUDA SDK) and `libspirv-nvptx64--nvidiacl.bc`
-(built by the libclc project).
+`libdevice.bc` (provided by the CUDA SDK) and `libspirv-nvptx64--nvidiacl.bc` variants
+(built by the libclc project). `libspirv-nvptx64--nvidiacl.bc` is not used directly. 
+Instead it is used to generate remangled variants 
+`remangled-l64-signed_char.libspirv-nvptx64--nvidiacl.bc` and
+`remangled-l32-signed_char.libspirv-nvptx64--nvidiacl.bc` to handle primitive type
+differences between Linux and Windows.
 
 ##### Device code post-link step for CUDA
 
@@ -568,6 +572,19 @@ path in SYCL kernels.
 
 ##### NVPTX Builtins
 
+Builtins are implemented in OpenCL C within libclc. OpenCL C treats `long` 
+types as 64 bit and has no `long long` types while Windows DPC++ treats `long`
+types like 32-bit integers and `long long` types like 64-bit integers. 
+Differences between the primitive types can cause applications to use 
+incompatible libclc built-ins. A remangler creates multiple libspriv files 
+with different remangled function names to support both Windows and Linux. 
+When building a SYCL application targeting the CUDA backend the driver 
+will link the device code with 
+`remangled-l32-signed_char.libspirv-nvptx64--nvidiacl.bc` if the host target is
+Windows or it will link the device code with
+`remangled-l64-signed_char.libspirv-nvptx64--nvidiacl.bc` if the host target is
+Linux.
+
 When the SYCL compiler is in device mode and targeting the NVPTX backend, the
 compiler exposes NVPTX builtins supported by clang.
 

sycl/doc/GetStartedGuide.md

@@ -148,18 +148,24 @@ python %DPCPP_HOME%\llvm\buildbot\compile.py
 
 There is experimental support for DPC++ for CUDA devices.
 
-To enable support for CUDA devices, follow the instructions for the Linux
-DPC++ toolchain, but add the `--cuda` flag to `configure.py`
+To enable support for CUDA devices, follow the instructions for the Linux or
+Windows DPC++ toolchain, but add the `--cuda` flag to `configure.py`. Note, 
+the CUDA backend has experimental Windows support, windows subsystem for 
+linux (WSL) is not needed to build and run the CUDA backend.
 
 Enabling this flag requires an installation of
 [CUDA 10.2](https://developer.nvidia.com/cuda-10.2-download-archive) on
 the system, refer to
-[NVIDIA CUDA Installation Guide for Linux](https://docs.nvidia.com/cuda/cuda-installation-guide-linux/index.html).
+[NVIDIA CUDA Installation Guide for Linux](https://docs.nvidia.com/cuda/cuda-installation-guide-linux/index.html)
+or
+[NVIDIA CUDA Installation Guide for Windows](https://docs.nvidia.com/cuda/cuda-installation-guide-microsoft-windows/index.html)
 
 Currently, the only combination tested is Ubuntu 18.04 with CUDA 10.2 using
-a Titan RTX GPU (SM 71), but it should work on any GPU compatible with SM 50 or
-above. The default SM for the NVIDIA CUDA backend is 5.0. Users can specify
-lower values, but some features may not be supported.
+a Titan RTX GPU (SM 71). The CUDA backend should work on Windows or Linux 
+operating systems with any GPU compatible with SM 50 or above. The default 
+SM for the NVIDIA CUDA backend is 5.0. Users can specify lower values, 
+but some features may not be supported. Windows CUDA support is experimental
+as it is not currently tested on the CI.
 
 **Non-standard CUDA location**
 

sycl/include/CL/sycl/aspects.hpp

@@ -20,8 +20,8 @@ enum class aspect {
   custom = 4,
   fp16 = 5,
   fp64 = 6,
-  int64_base_atomics = 7,
-  int64_extended_atomics = 8,
+  int64_base_atomics __SYCL2020_DEPRECATED("use atomic64 instead") = 7,
+  int64_extended_atomics __SYCL2020_DEPRECATED("use atomic64 instead") = 8,
   image = 9,
   online_compiler = 10,
   online_linker = 11,
@@ -47,6 +47,7 @@ enum class aspect {
   ext_intel_device_info_uuid = 29,
   ext_oneapi_srgb = 30,
   ext_oneapi_native_assert = 31,
+  host_debuggable = 32,
 };
 
 } // namespace sycl