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AaronBallmanAaronBallman
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[SYCL] Refactor the way we diagnose some SYCL attributes; mostly NFC (#3147)
This removes a helper method from some SYCL attributes which would provide the name of the attribute. This code wasn't needed because the diagnostics engine already knows how to print attributes by name. While making this change, some diagnostics are now properly quoted when they weren't previously. As a drive-by, I also noticed that the location of the diagnostics was wrong (it was diagnosing the start of the attribute range rather than the problematic attribute). This means that duplicate or conflicting attributes should be warning about the second attribute (the one causing the conflict) rather than the first attribute.
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5 files changed

+60
-105
lines changed

5 files changed

+60
-105
lines changed

‎clang/include/clang/Basic/Attr.td

Lines changed: 0 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1272,11 +1272,6 @@ def SYCLIntelUseStallEnableClusters : InheritableAttr {
12721272
let Spellings = [CXX11<"intel","use_stall_enable_clusters">];
12731273
let LangOpts = [SYCLIsHost, SYCLIsDevice];
12741274
let Subjects = SubjectList<[Function], ErrorDiag>;
1275-
let AdditionalMembers = [{
1276-
static const char *getName() {
1277-
return "stall_enable";
1278-
}
1279-
}];
12801275
let Documentation = [SYCLIntelUseStallEnableClustersAttrDocs];
12811276
}
12821277

@@ -1394,9 +1389,6 @@ def LoopUnrollHint : InheritableAttr {
13941389
let LangOpts = [SYCLIsDevice, SYCLIsHost];
13951390
let HasCustomTypeTransform = 1;
13961391
let AdditionalMembers = [{
1397-
static const char *getName() {
1398-
return "loop_unroll";
1399-
}
14001392
std::string getDiagnosticName(const PrintingPolicy &Policy) const {
14011393
std::string ValueName;
14021394
llvm::raw_string_ostream OS(ValueName);
@@ -1820,9 +1812,6 @@ def SYCLIntelFPGAIVDep : Attr {
18201812
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18211813
let HasCustomTypeTransform = 1;
18221814
let AdditionalMembers = [{
1823-
static const char *getName() {
1824-
return "ivdep";
1825-
}
18261815
bool isDependent() const {
18271816
return (getSafelenExpr() &&
18281817
getSafelenExpr()->isInstantiationDependent()) ||
@@ -1863,11 +1852,6 @@ def SYCLIntelFPGAII : Attr {
18631852
let Args = [ExprArgument<"IntervalExpr">];
18641853
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18651854
let HasCustomTypeTransform = 1;
1866-
let AdditionalMembers = [{
1867-
static const char *getName() {
1868-
return "ii";
1869-
}
1870-
}];
18711855
let Documentation = [SYCLIntelFPGAIIAttrDocs];
18721856
}
18731857

@@ -1877,11 +1861,6 @@ def SYCLIntelFPGAMaxConcurrency : Attr {
18771861
let Args = [ExprArgument<"NThreadsExpr">];
18781862
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18791863
let HasCustomTypeTransform = 1;
1880-
let AdditionalMembers = [{
1881-
static const char *getName() {
1882-
return "max_concurrency";
1883-
}
1884-
}];
18851864
let Documentation = [SYCLIntelFPGAMaxConcurrencyAttrDocs];
18861865
}
18871866

@@ -1891,11 +1870,6 @@ def SYCLIntelFPGALoopCoalesce : Attr {
18911870
let Args = [ExprArgument<"NExpr">];
18921871
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18931872
let HasCustomTypeTransform = 1;
1894-
let AdditionalMembers = [{
1895-
static const char *getName() {
1896-
return "loop_coalesce";
1897-
}
1898-
}];
18991873
let Documentation = [SYCLIntelFPGALoopCoalesceAttrDocs];
19001874
}
19011875

@@ -1904,11 +1878,6 @@ def SYCLIntelFPGADisableLoopPipelining : Attr {
19041878
CXX11<"intel","disable_loop_pipelining">];
19051879
let LangOpts = [SYCLIsDevice, SYCLIsHost];
19061880
let HasCustomTypeTransform = 1;
1907-
let AdditionalMembers = [{
1908-
static const char *getName() {
1909-
return "disable_loop_pipelining";
1910-
}
1911-
}];
19121881
let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs];
19131882
}
19141883

@@ -1918,11 +1887,6 @@ def SYCLIntelFPGAMaxInterleaving : Attr {
19181887
let Args = [ExprArgument<"NExpr">];
19191888
let LangOpts = [SYCLIsDevice, SYCLIsHost];
19201889
let HasCustomTypeTransform = 1;
1921-
let AdditionalMembers = [{
1922-
static const char *getName() {
1923-
return "max_interleaving";
1924-
}
1925-
}];
19261890
let Documentation = [SYCLIntelFPGAMaxInterleavingAttrDocs];
19271891
}
19281892

@@ -1932,23 +1896,13 @@ def SYCLIntelFPGASpeculatedIterations : Attr {
19321896
let Args = [ExprArgument<"NExpr">];
19331897
let LangOpts = [SYCLIsDevice, SYCLIsHost];
19341898
let HasCustomTypeTransform = 1;
1935-
let AdditionalMembers = [{
1936-
static const char *getName() {
1937-
return "speculated_iterations";
1938-
}
1939-
}];
19401899
let Documentation = [SYCLIntelFPGASpeculatedIterationsAttrDocs];
19411900
}
19421901

19431902
def SYCLIntelFPGANofusion : Attr {
19441903
let Spellings = [CXX11<"intel","nofusion">];
19451904
let LangOpts = [SYCLIsDevice, SYCLIsHost];
19461905
let HasCustomTypeTransform = 1;
1947-
let AdditionalMembers = [{
1948-
static const char *getName() {
1949-
return "nofusion";
1950-
}
1951-
}];
19521906
let Documentation = [SYCLIntelFPGANofusionAttrDocs];
19531907
}
19541908

‎clang/include/clang/Basic/DiagnosticSemaKinds.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ def err_intel_fpga_reg_limitations : Error <
135135
def illegal_type_declared_here : Note<
136136
"field with illegal type declared here">;
137137
def err_sycl_loop_attr_duplication : Error<
138-
"duplicate %select{unroll|Intel FPGA}0 loop attribute '%1'">;
138+
"duplicate %select{unroll|Intel FPGA}0 loop attribute %1">;
139139
def err_loop_unroll_compatibility : Error<
140140
"incompatible loop unroll instructions: '%0' and '%1'">;
141141
def err_pipe_attribute_arg_not_allowed : Error<

‎clang/lib/Sema/SemaStmtAttr.cpp

Lines changed: 43 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -593,19 +593,17 @@ CheckForIncompatibleAttributes(Sema &S,
593593
}
594594

595595
template <typename LoopAttrT>
596-
static void CheckForDuplicationSYCLLoopAttribute(
597-
Sema &S, const SmallVectorImpl<const Attr *> &Attrs, SourceRange Range,
598-
bool isIntelFPGAAttr = true) {
596+
static void
597+
CheckForDuplicationSYCLLoopAttribute(Sema &S,
598+
const SmallVectorImpl<const Attr *> &Attrs,
599+
bool isIntelFPGAAttr = true) {
599600
const LoopAttrT *LoopAttr = nullptr;
600601

601602
for (const auto *I : Attrs) {
602-
if (LoopAttr) {
603-
if (isa<LoopAttrT>(I)) {
604-
SourceLocation Loc = Range.getBegin();
605-
// Cannot specify same type of attribute twice.
606-
S.Diag(Loc, diag::err_sycl_loop_attr_duplication)
607-
<< isIntelFPGAAttr << LoopAttr->getName();
608-
}
603+
if (LoopAttr && isa<LoopAttrT>(I)) {
604+
// Cannot specify same type of attribute twice.
605+
S.Diag(I->getLocation(), diag::err_sycl_loop_attr_duplication)
606+
<< isIntelFPGAAttr << LoopAttr;
609607
}
610608
if (isa<LoopAttrT>(I))
611609
LoopAttr = cast<LoopAttrT>(I);
@@ -616,55 +614,58 @@ static void CheckForDuplicationSYCLLoopAttribute(
616614
/// declaration. Returns true if diagnosed.
617615
template <typename LoopAttrT, typename LoopAttrT2>
618616
static void CheckMutualExclusionSYCLLoopAttribute(
619-
Sema &S, const SmallVectorImpl<const Attr *> &Attrs, SourceRange Range) {
620-
const LoopAttrT *LoopAttr = nullptr;
621-
const LoopAttrT2 *LoopAttr2 = nullptr;
617+
Sema &S, const SmallVectorImpl<const Attr *> &Attrs) {
618+
std::pair<bool, bool> SeenAttrs;
619+
const Attr *FirstSeen = nullptr;
622620

623621
for (const auto *I : Attrs) {
622+
// Remember the first attribute of the problematic type so that we can
623+
// potentially diagnose it later.
624+
if (!FirstSeen && isa<LoopAttrT, LoopAttrT2>(I))
625+
FirstSeen = I;
626+
627+
// Remember if we've seen either of the attribute types.
624628
if (isa<LoopAttrT>(I))
625-
LoopAttr = cast<LoopAttrT>(I);
626-
if (isa<LoopAttrT2>(I))
627-
LoopAttr2 = cast<LoopAttrT2>(I);
628-
if (LoopAttr && LoopAttr2) {
629-
S.Diag(Range.getBegin(), diag::err_attributes_are_not_compatible)
630-
<< LoopAttr->getSpelling() << LoopAttr2->getSpelling();
631-
}
629+
SeenAttrs.first = true;
630+
else if (isa<LoopAttrT2>(I))
631+
SeenAttrs.second = true;
632+
633+
// If we've seen both of the attribute types, then diagnose them both.
634+
if (SeenAttrs.first && SeenAttrs.second)
635+
S.Diag(I->getLocation(), diag::err_attributes_are_not_compatible)
636+
<< FirstSeen << I;
632637
}
633638
}
634639

635640
static void CheckForIncompatibleSYCLLoopAttributes(
636-
Sema &S, const SmallVectorImpl<const Attr *> &Attrs, SourceRange Range) {
637-
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAIIAttr>(S, Attrs, Range);
638-
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAMaxConcurrencyAttr>(
639-
S, Attrs, Range);
640-
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGALoopCoalesceAttr>(S, Attrs,
641-
Range);
641+
Sema &S, const SmallVectorImpl<const Attr *> &Attrs) {
642+
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAIIAttr>(S, Attrs);
643+
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAMaxConcurrencyAttr>(S,
644+
Attrs);
645+
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGALoopCoalesceAttr>(S, Attrs);
642646
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGADisableLoopPipeliningAttr>(
643-
S, Attrs, Range);
644-
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAMaxInterleavingAttr>(
645-
S, Attrs, Range);
647+
S, Attrs);
648+
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAMaxInterleavingAttr>(S,
649+
Attrs);
646650
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGASpeculatedIterationsAttr>(
647-
S, Attrs, Range);
648-
CheckForDuplicationSYCLLoopAttribute<LoopUnrollHintAttr>(S, Attrs, Range,
649-
false);
651+
S, Attrs);
652+
CheckForDuplicationSYCLLoopAttribute<LoopUnrollHintAttr>(S, Attrs, false);
650653
CheckMutualExclusionSYCLLoopAttribute<SYCLIntelFPGADisableLoopPipeliningAttr,
651654
SYCLIntelFPGAMaxInterleavingAttr>(
652-
S, Attrs, Range);
655+
S, Attrs);
653656
CheckMutualExclusionSYCLLoopAttribute<SYCLIntelFPGADisableLoopPipeliningAttr,
654657
SYCLIntelFPGASpeculatedIterationsAttr>(
655-
S, Attrs, Range);
658+
S, Attrs);
656659
CheckMutualExclusionSYCLLoopAttribute<SYCLIntelFPGADisableLoopPipeliningAttr,
657-
SYCLIntelFPGAIIAttr>(S, Attrs, Range);
660+
SYCLIntelFPGAIIAttr>(S, Attrs);
658661
CheckMutualExclusionSYCLLoopAttribute<SYCLIntelFPGADisableLoopPipeliningAttr,
659-
SYCLIntelFPGAIVDepAttr>(S, Attrs,
660-
Range);
662+
SYCLIntelFPGAIVDepAttr>(S, Attrs);
661663
CheckMutualExclusionSYCLLoopAttribute<SYCLIntelFPGADisableLoopPipeliningAttr,
662-
SYCLIntelFPGAMaxConcurrencyAttr>(
663-
S, Attrs, Range);
664+
SYCLIntelFPGAMaxConcurrencyAttr>(S,
665+
Attrs);
664666

665667
CheckRedundantSYCLIntelFPGAIVDepAttrs(S, Attrs);
666-
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGANofusionAttr>(S, Attrs,
667-
Range);
668+
CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGANofusionAttr>(S, Attrs);
668669
}
669670

670671
void CheckForIncompatibleUnrollHintAttributes(
@@ -814,7 +815,7 @@ StmtResult Sema::ProcessStmtAttributes(Stmt *S,
814815
}
815816

816817
CheckForIncompatibleAttributes(*this, Attrs);
817-
CheckForIncompatibleSYCLLoopAttributes(*this, Attrs, Range);
818+
CheckForIncompatibleSYCLLoopAttributes(*this, Attrs);
818819
CheckForIncompatibleUnrollHintAttributes(*this, Attrs, Range);
819820

820821
if (Attrs.empty())

‎clang/test/SemaSYCL/intel-fpga-loops.cpp

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -221,34 +221,34 @@ void zoo() {
221221
[[intel::ivdep(4)]] for (int i = 0; i != 10; ++i)
222222
a[i] = 0;
223223
[[intel::max_concurrency(2)]]
224-
// expected-error@-1 {{duplicate Intel FPGA loop attribute 'max_concurrency'}}
224+
// expected-error@+1 {{duplicate Intel FPGA loop attribute 'max_concurrency'}}
225225
[[intel::max_concurrency(2)]] for (int i = 0; i != 10; ++i)
226226
a[i] = 0;
227227
[[intel::ii(2)]]
228-
// expected-error@-1 {{duplicate Intel FPGA loop attribute 'ii'}}
228+
// expected-error@+1 {{duplicate Intel FPGA loop attribute 'ii'}}
229229
[[intel::ii(2)]] for (int i = 0; i != 10; ++i)
230230
a[i] = 0;
231231
[[intel::ii(2)]]
232-
// expected-error@-1 {{duplicate Intel FPGA loop attribute 'ii'}}
232+
// expected-error@+2 {{duplicate Intel FPGA loop attribute 'ii'}}
233233
[[intel::max_concurrency(2)]]
234234
[[intel::ii(2)]] for (int i = 0; i != 10; ++i)
235235
a[i] = 0;
236236
[[intel::disable_loop_pipelining]]
237-
// expected-error@-1 {{duplicate Intel FPGA loop attribute 'disable_loop_pipelining'}}
237+
// expected-error@+1 {{duplicate Intel FPGA loop attribute 'disable_loop_pipelining'}}
238238
[[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i)
239239
a[i] = 0;
240240
[[intel::loop_coalesce(2)]]
241-
// expected-error@-1 {{duplicate Intel FPGA loop attribute 'loop_coalesce'}}
241+
// expected-error@+2 {{duplicate Intel FPGA loop attribute 'loop_coalesce'}}
242242
[[intel::max_interleaving(1)]]
243243
[[intel::loop_coalesce]] for (int i = 0; i != 10; ++i)
244244
a[i] = 0;
245245
[[intel::max_interleaving(1)]]
246-
// expected-error@-1 {{duplicate Intel FPGA loop attribute 'max_interleaving'}}
246+
// expected-error@+2 {{duplicate Intel FPGA loop attribute 'max_interleaving'}}
247247
[[intel::speculated_iterations(1)]]
248248
[[intel::max_interleaving(4)]] for (int i = 0; i != 10; ++i)
249249
a[i] = 0;
250250
[[intel::speculated_iterations(1)]]
251-
// expected-error@-1 {{duplicate Intel FPGA loop attribute 'speculated_iterations'}}
251+
// expected-error@+2 {{duplicate Intel FPGA loop attribute 'speculated_iterations'}}
252252
[[intel::loop_coalesce]]
253253
[[intel::speculated_iterations(2)]] for (int i = 0; i != 10; ++i)
254254
a[i] = 0;
@@ -301,7 +301,7 @@ void zoo() {
301301
a[i] = 0;
302302

303303
[[intel::nofusion]]
304-
// expected-error@-1 {{duplicate Intel FPGA loop attribute 'nofusion'}}
304+
// expected-error@+1 {{duplicate Intel FPGA loop attribute 'nofusion'}}
305305
[[intel::nofusion]] for (int i = 0; i != 10; ++i)
306306
a[i] = 0;
307307
}
@@ -313,23 +313,23 @@ void loop_attrs_compatibility() {
313313
[[intel::disable_loop_pipelining]]
314314
[[intel::loop_coalesce]] for (int i = 0; i != 10; ++i)
315315
a[i] = 0;
316-
// expected-error@+1 {{disable_loop_pipelining and max_interleaving attributes are not compatible}}
316+
// expected-error@+2 {{'disable_loop_pipelining' and 'max_interleaving' attributes are not compatible}}
317317
[[intel::disable_loop_pipelining]]
318318
[[intel::max_interleaving(0)]] for (int i = 0; i != 10; ++i)
319319
a[i] = 0;
320-
// expected-error@+1 {{disable_loop_pipelining and speculated_iterations attributes are not compatible}}
320+
// expected-error@+2 {{'speculated_iterations' and 'disable_loop_pipelining' attributes are not compatible}}
321321
[[intel::speculated_iterations(0)]]
322322
[[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i)
323323
a[i] = 0;
324-
// expected-error@+1 {{disable_loop_pipelining and max_concurrency attributes are not compatible}}
324+
// expected-error@+2 {{'disable_loop_pipelining' and 'max_concurrency' attributes are not compatible}}
325325
[[intel::disable_loop_pipelining]]
326326
[[intel::max_concurrency(0)]] for (int i = 0; i != 10; ++i)
327327
a[i] = 0;
328-
// expected-error@+1 {{disable_loop_pipelining and ii attributes are not compatible}}
328+
// expected-error@+2 {{'ii' and 'disable_loop_pipelining' attributes are not compatible}}
329329
[[intel::ii(10)]]
330330
[[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i)
331331
a[i] = 0;
332-
// expected-error@+1 {{disable_loop_pipelining and ivdep attributes are not compatible}}
332+
// expected-error@+2 {{'disable_loop_pipelining' and 'ivdep' attributes are not compatible}}
333333
[[intel::disable_loop_pipelining]]
334334
[[intel::ivdep]] for (int i = 0; i != 10; ++i)
335335
a[i] = 0;
@@ -378,7 +378,7 @@ void ii_dependent() {
378378
[[intel::ii(C)]] for (int i = 0; i != 10; ++i)
379379
a[i] = 0;
380380

381-
// expected-error@+1 {{duplicate Intel FPGA loop attribute 'ii'}}
381+
// expected-error@+2 {{duplicate Intel FPGA loop attribute 'ii'}}
382382
[[intel::ii(A)]]
383383
[[intel::ii(B)]] for (int i = 0; i != 10; ++i)
384384
a[i] = 0;
@@ -391,7 +391,7 @@ void max_concurrency_dependent() {
391391
[[intel::max_concurrency(C)]] for (int i = 0; i != 10; ++i)
392392
a[i] = 0;
393393

394-
// expected-error@+1 {{duplicate Intel FPGA loop attribute 'max_concurrency'}}
394+
// expected-error@+2 {{duplicate Intel FPGA loop attribute 'max_concurrency'}}
395395
[[intel::max_concurrency(A)]]
396396
[[intel::max_concurrency(B)]] for (int i = 0; i != 10; ++i)
397397
a[i] = 0;

‎clang/test/SemaSYCL/loop_unroll.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ void foo() {
2727
[[clang::loop_unroll("str123")]]
2828
for (int i = 0; i < 10; ++i);
2929

30-
// expected-error@+1 {{duplicate unroll loop attribute 'loop_unroll'}}
30+
// expected-error@+2 {{duplicate unroll loop attribute 'loop_unroll'}}
3131
[[clang::loop_unroll(2)]]
3232
[[clang::loop_unroll(4)]]
3333
for (int i = 0; i < 10; ++i);

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