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Ansuelbebarino
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clk: en7523: Rework clock handling for different clock numbers
Airoha EN7581 SoC have additional clock compared to EN7523 but current driver permits to only support up to EN7523 clock numbers. To handle this, rework the clock handling and permit to declare the clocks number in match_data and alloca clk_data based on the compatible match_data. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20250113231030.6735-2-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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drivers/clk/clk-en7523.c

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,7 @@ struct en_rst_data {
7575
};
7676

7777
struct en_clk_soc_data {
78+
u32 num_clocks;
7879
const struct clk_ops pcie_ops;
7980
int (*hw_init)(struct platform_device *pdev,
8081
struct clk_hw_onecell_data *clk_data);
@@ -504,8 +505,6 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
504505
u32 rate;
505506
int i;
506507

507-
clk_data->num = EN7523_NUM_CLOCKS;
508-
509508
for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
510509
const struct en_clk_desc *desc = &en7523_base_clks[i];
511510
u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg;
@@ -587,8 +586,6 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat
587586

588587
hw = en7523_register_pcie_clk(dev, base);
589588
clk_data->hws[EN7523_CLK_PCIE] = hw;
590-
591-
clk_data->num = EN7523_NUM_CLOCKS;
592589
}
593590

594591
static int en7523_reset_update(struct reset_controller_dev *rcdev,
@@ -702,13 +699,15 @@ static int en7523_clk_probe(struct platform_device *pdev)
702699
struct clk_hw_onecell_data *clk_data;
703700
int r;
704701

702+
soc_data = device_get_match_data(&pdev->dev);
703+
705704
clk_data = devm_kzalloc(&pdev->dev,
706-
struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
705+
struct_size(clk_data, hws, soc_data->num_clocks),
707706
GFP_KERNEL);
708707
if (!clk_data)
709708
return -ENOMEM;
710709

711-
soc_data = device_get_match_data(&pdev->dev);
710+
clk_data->num = soc_data->num_clocks;
712711
r = soc_data->hw_init(pdev, clk_data);
713712
if (r)
714713
return r;
@@ -717,6 +716,7 @@ static int en7523_clk_probe(struct platform_device *pdev)
717716
}
718717

719718
static const struct en_clk_soc_data en7523_data = {
719+
.num_clocks = ARRAY_SIZE(en7523_base_clks) + 1,
720720
.pcie_ops = {
721721
.is_enabled = en7523_pci_is_enabled,
722722
.prepare = en7523_pci_prepare,
@@ -726,6 +726,8 @@ static const struct en_clk_soc_data en7523_data = {
726726
};
727727

728728
static const struct en_clk_soc_data en7581_data = {
729+
/* We increment num_clocks by 1 to account for additional PCIe clock */
730+
.num_clocks = ARRAY_SIZE(en7581_base_clks) + 1,
729731
.pcie_ops = {
730732
.is_enabled = en7581_pci_is_enabled,
731733
.enable = en7581_pci_enable,

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