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Merge tag 'riscv-sophgo-clk-for-v6.16' of https://github.com/sophgo/linux into clk-sophgo
Pull RISC-V Sophgo clk driver updates from Chen Wang: - Replace compatible for Sophgo CV1800 series SoC - Add clock support for Sophgo SG2044 * tag 'riscv-sophgo-clk-for-v6.16' of https://github.com/sophgo/linux: clk: sophgo: Add clock controller support for SG2044 SoC clk: sophgo: Add PLL clock controller support for SG2044 SoC dt-bindings: clock: sophgo: add clock controller for SG2044 dt-bindings: soc: sophgo: Add SG2044 top syscon device clk: sophgo: Add support for newly added precise compatible dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC
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‎Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml

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@@ -11,10 +11,18 @@ maintainers:
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properties:
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compatible:
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enum:
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- sophgo,cv1800-clk
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- sophgo,cv1810-clk
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- sophgo,sg2000-clk
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oneOf:
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- enum:
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- sophgo,cv1800b-clk
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- sophgo,cv1812h-clk
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- sophgo,sg2000-clk
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- items:
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- const: sophgo,sg2002-clk
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- const: sophgo,sg2000-clk
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- const: sophgo,cv1800-clk
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deprecated: true
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- const: sophgo,cv1810-clk
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deprecated: true
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reg:
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maxItems: 1

‎Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sophgo SG2044 Clock Controller
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maintainers:
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- Inochi Amaoto <inochiama@gmail.com>
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description: |
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The Sophgo SG2044 clock controller requires an external oscillator
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as input clock.
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All available clocks are defined as preprocessor macros in
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include/dt-bindings/clock/sophgo,sg2044-clk.h
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properties:
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compatible:
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const: sophgo,sg2044-clk
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reg:
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maxItems: 1
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clocks:
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items:
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- description: fpll0
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- description: fpll1
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- description: fpll2
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- description: dpll0
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- description: dpll1
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- description: dpll2
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- description: dpll3
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- description: dpll4
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- description: dpll5
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- description: dpll6
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- description: dpll7
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- description: mpll0
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- description: mpll1
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- description: mpll2
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- description: mpll3
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- description: mpll4
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- description: mpll5
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clock-names:
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items:
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- const: fpll0
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- const: fpll1
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- const: fpll2
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- const: dpll0
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- const: dpll1
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- const: dpll2
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- const: dpll3
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- const: dpll4
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- const: dpll5
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- const: dpll6
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- const: dpll7
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- const: mpll0
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- const: mpll1
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- const: mpll2
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- const: mpll3
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- const: mpll4
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- const: mpll5
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sophgo,sg2044-pll.h>
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clock-controller@50002000 {
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compatible = "sophgo,sg2044-clk";
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reg = <0x50002000 0x1000>;
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#clock-cells = <1>;
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clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
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<&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
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<&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
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<&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
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<&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
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<&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
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<&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
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<&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
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<&syscon CLK_MPLL5>;
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clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
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"dpll1", "dpll2", "dpll3", "dpll4",
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"dpll5", "dpll6", "dpll7", "mpll0",
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"mpll1", "mpll2", "mpll3", "mpll4",
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"mpll5";
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};

‎Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-top-syscon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sophgo SG2044 SoC TOP system controller
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maintainers:
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- Inochi Amaoto <inochiama@gmail.com>
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description:
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The Sophgo SG2044 TOP system controller is a hardware block grouping
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multiple small functions, such as clocks and some other internal
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function.
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properties:
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compatible:
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items:
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- const: sophgo,sg2044-top-syscon
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- const: syscon
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/sophgo,sg2044-pll.h> for valid clock.
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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syscon@50000000 {
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compatible = "sophgo,sg2044-top-syscon", "syscon";
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reg = <0x50000000 0x1000>;
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#clock-cells = <1>;
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clocks = <&osc>;
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};

‎drivers/clk/sophgo/Kconfig

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@@ -37,3 +37,22 @@ config CLK_SOPHGO_SG2042_RPGATE
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This clock IP depends on SG2042 Clock Generator because it uses
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clock from Clock Generator IP as input.
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This driver provides Gate function for RP.
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config CLK_SOPHGO_SG2044
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tristate "Sophgo SG2044 clock controller support"
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depends on ARCH_SOPHGO || COMPILE_TEST
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help
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This driver supports the clock controller on the Sophgo SG2044
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SoC. This controller requires mulitple PLL clock as input.
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This clock control provides PLL clocks and common clock function
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for various IPs on the SoC.
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config CLK_SOPHGO_SG2044_PLL
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tristate "Sophgo SG2044 PLL clock controller support"
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depends on ARCH_SOPHGO || COMPILE_TEST
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select MFD_SYSCON
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select REGMAP_MMIO
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help
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This driver supports the PLL clock controller on the Sophgo
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SG2044 SoC. This controller requires 25M oscillator as input.
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This clock control provides PLL clocks on the SoC.

‎drivers/clk/sophgo/Makefile

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@@ -9,3 +9,5 @@ clk-sophgo-cv1800-y += clk-cv18xx-pll.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL) += clk-sg2042-pll.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE) += clk-sg2042-rpgate.o
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obj-$(CONFIG_CLK_SOPHGO_SG2044) += clk-sg2044.o
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obj-$(CONFIG_CLK_SOPHGO_SG2044_PLL) += clk-sg2044-pll.o

‎drivers/clk/sophgo/clk-cv1800.c

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@@ -1519,7 +1519,9 @@ static int cv1800_clk_probe(struct platform_device *pdev)
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static const struct of_device_id cv1800_clk_ids[] = {
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{ .compatible = "sophgo,cv1800-clk", .data = &cv1800_desc },
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{ .compatible = "sophgo,cv1800b-clk", .data = &cv1800_desc },
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{ .compatible = "sophgo,cv1810-clk", .data = &cv1810_desc },
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{ .compatible = "sophgo,cv1812h-clk", .data = &cv1810_desc },
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{ .compatible = "sophgo,sg2000-clk", .data = &sg2000_desc },
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{ }
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};

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