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lines changed Original file line number Diff line number Diff line change @@ -38,6 +38,15 @@ config CLK_SOPHGO_SG2042_RPGATE
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clock from Clock Generator IP as input.
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This driver provides Gate function for RP.
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+ config CLK_SOPHGO_SG2044
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+ tristate "Sophgo SG2044 clock controller support"
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+ depends on ARCH_SOPHGO || COMPILE_TEST
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+ help
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+ This driver supports the clock controller on the Sophgo SG2044
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+ SoC. This controller requires mulitple PLL clock as input.
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+ This clock control provides PLL clocks and common clock function
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+ for various IPs on the SoC.
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+
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config CLK_SOPHGO_SG2044_PLL
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tristate "Sophgo SG2044 PLL clock controller support"
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depends on ARCH_SOPHGO || COMPILE_TEST
Original file line number Diff line number Diff line change @@ -9,4 +9,5 @@ clk-sophgo-cv1800-y += clk-cv18xx-pll.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL) += clk-sg2042-pll.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE) += clk-sg2042-rpgate.o
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+ obj-$(CONFIG_CLK_SOPHGO_SG2044) += clk-sg2044.o
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obj-$(CONFIG_CLK_SOPHGO_SG2044_PLL) += clk-sg2044-pll.o
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