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Merge tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the RZ/G3E (R9A09G047) SoC - Add Module Stop (MSTOP) support on RZ/V2H - Add Image Signal Processor helper block (FCPVX and VSPX) clocks on R-Car V4H SoC - Add System Controller (SYS) reset and Generic Interrupt Controller (GIC) clock and reset entries on RZ/V2H * tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard clk: renesas: r9a09g057: Add clock and reset entries for GIC clk: renesas: r9a09g057: Add reset entry for SYS clk: renesas: r8a779g0: Add VSPX clocks clk: renesas: r8a779g0: Add FCPVX clocks clk: renesas: r9a09g047: Add I2C clocks/resets clk: renesas: r9a09g047: Add CA55 core clocks clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: rzv2h: Add MSTOP support dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
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‎Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,19 +4,22 @@
44
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

7-
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
7+
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
88

99
maintainers:
1010
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
1111

1212
description:
13-
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
14-
and control of clock signals for the IP modules, generation and control of resets,
15-
and control over booting, low power consumption and power supply domains.
13+
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
14+
generation and control of clock signals for the IP modules, generation and
15+
control of resets, and control over booting, low power consumption and power
16+
supply domains.
1617

1718
properties:
1819
compatible:
19-
const: renesas,r9a09g057-cpg
20+
enum:
21+
- renesas,r9a09g047-cpg # RZ/G3E
22+
- renesas,r9a09g057-cpg # RZ/V2H
2023

2124
reg:
2225
maxItems: 1
@@ -37,7 +40,7 @@ properties:
3740
description: |
3841
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
3942
and a core clock reference, as defined in
40-
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
43+
<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
4144
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
4245
a module number. The module number is calculated as the CLKON register
4346
offset index multiplied by 16, plus the actual bit in the register

‎Documentation/devicetree/bindings/soc/renesas/renesas.yaml

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -525,6 +525,23 @@ properties:
525525
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
526526
- const: renesas,r9a09g011
527527

528+
- description: RZ/G3E (R9A09G047)
529+
items:
530+
- enum:
531+
- renesas,smarc2-evk # RZ SMARC Carrier-II EVK
532+
- enum:
533+
- renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
534+
- enum:
535+
- renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
536+
- renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
537+
- renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
538+
- renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
539+
- renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
540+
- renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
541+
- renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
542+
- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
543+
- const: renesas,r9a09g047
544+
528545
- description: RZ/V2H(P) (R9A09G057)
529546
items:
530547
- enum:

‎drivers/clk/renesas/Kconfig

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ config CLK_RENESAS
4040
select CLK_R9A07G054 if ARCH_R9A07G054
4141
select CLK_R9A08G045 if ARCH_R9A08G045
4242
select CLK_R9A09G011 if ARCH_R9A09G011
43+
select CLK_R9A09G047 if ARCH_R9A09G047
4344
select CLK_R9A09G057 if ARCH_R9A09G057
4445
select CLK_SH73A0 if ARCH_SH73A0
4546

@@ -194,6 +195,10 @@ config CLK_R9A09G011
194195
bool "RZ/V2M clock support" if COMPILE_TEST
195196
select CLK_RZG2L
196197

198+
config CLK_R9A09G047
199+
bool "RZ/G3E clock support" if COMPILE_TEST
200+
select CLK_RZV2H
201+
197202
config CLK_R9A09G057
198203
bool "RZ/V2H(P) clock support" if COMPILE_TEST
199204
select CLK_RZV2H
@@ -234,7 +239,7 @@ config CLK_RZG2L
234239
select RESET_CONTROLLER
235240

236241
config CLK_RZV2H
237-
bool "RZ/V2H(P) family clock support" if COMPILE_TEST
242+
bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST
238243
select RESET_CONTROLLER
239244

240245
config CLK_RENESAS_VBATTB

‎drivers/clk/renesas/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
3737
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
3838
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
3939
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
40+
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
4041
obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
4142
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
4243

‎drivers/clk/renesas/r8a779g0-cpg-mssr.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -238,6 +238,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
238238
DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
239239
DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
240240
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
241+
DEF_MOD("vspx0", 1028, R8A779G0_CLK_S0D1_VIO),
242+
DEF_MOD("vspx1", 1029, R8A779G0_CLK_S0D1_VIO),
243+
DEF_MOD("fcpvx0", 1100, R8A779G0_CLK_S0D1_VIO),
244+
DEF_MOD("fcpvx1", 1101, R8A779G0_CLK_S0D1_VIO),
241245
DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
242246
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
243247
DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),

‎drivers/clk/renesas/r9a09g047-cpg.c

Lines changed: 150 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,150 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Renesas RZ/G3E CPG driver
4+
*
5+
* Copyright (C) 2024 Renesas Electronics Corp.
6+
*/
7+
8+
#include <linux/clk-provider.h>
9+
#include <linux/device.h>
10+
#include <linux/init.h>
11+
#include <linux/kernel.h>
12+
13+
#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
14+
15+
#include "rzv2h-cpg.h"
16+
17+
enum clk_ids {
18+
/* Core Clock Outputs exported to DT */
19+
LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK,
20+
21+
/* External Input Clocks */
22+
CLK_AUDIO_EXTAL,
23+
CLK_RTXIN,
24+
CLK_QEXTAL,
25+
26+
/* PLL Clocks */
27+
CLK_PLLCM33,
28+
CLK_PLLCLN,
29+
CLK_PLLDTY,
30+
CLK_PLLCA55,
31+
32+
/* Internal Core Clocks */
33+
CLK_PLLCM33_DIV16,
34+
CLK_PLLCLN_DIV16,
35+
CLK_PLLDTY_ACPU,
36+
CLK_PLLDTY_ACPU_DIV4,
37+
38+
/* Module Clocks */
39+
MOD_CLK_BASE,
40+
};
41+
42+
static const struct clk_div_table dtable_1_8[] = {
43+
{0, 1},
44+
{1, 2},
45+
{2, 4},
46+
{3, 8},
47+
{0, 0},
48+
};
49+
50+
static const struct clk_div_table dtable_2_64[] = {
51+
{0, 2},
52+
{1, 4},
53+
{2, 8},
54+
{3, 16},
55+
{4, 64},
56+
{0, 0},
57+
};
58+
59+
static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
60+
/* External Clock Inputs */
61+
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
62+
DEF_INPUT("rtxin", CLK_RTXIN),
63+
DEF_INPUT("qextal", CLK_QEXTAL),
64+
65+
/* PLL Clocks */
66+
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
67+
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
68+
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
69+
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
70+
71+
/* Internal Core Clocks */
72+
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
73+
74+
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
75+
76+
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
77+
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
78+
79+
/* Core Clocks */
80+
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
81+
DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
82+
CDDIV1_DIVCTL0, dtable_1_8),
83+
DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55,
84+
CDDIV1_DIVCTL1, dtable_1_8),
85+
DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55,
86+
CDDIV1_DIVCTL2, dtable_1_8),
87+
DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,
88+
CDDIV1_DIVCTL3, dtable_1_8),
89+
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
90+
};
91+
92+
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
93+
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
94+
BUS_MSTOP(3, BIT(5))),
95+
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
96+
BUS_MSTOP(3, BIT(14))),
97+
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
98+
BUS_MSTOP(3, BIT(13))),
99+
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
100+
BUS_MSTOP(1, BIT(1))),
101+
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
102+
BUS_MSTOP(1, BIT(2))),
103+
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
104+
BUS_MSTOP(1, BIT(3))),
105+
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
106+
BUS_MSTOP(1, BIT(4))),
107+
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
108+
BUS_MSTOP(1, BIT(5))),
109+
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
110+
BUS_MSTOP(1, BIT(6))),
111+
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
112+
BUS_MSTOP(1, BIT(7))),
113+
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
114+
BUS_MSTOP(1, BIT(8))),
115+
};
116+
117+
static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
118+
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
119+
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
120+
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
121+
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
122+
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
123+
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
124+
DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
125+
DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
126+
DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
127+
DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
128+
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
129+
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
130+
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
131+
};
132+
133+
const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
134+
/* Core Clocks */
135+
.core_clks = r9a09g047_core_clks,
136+
.num_core_clks = ARRAY_SIZE(r9a09g047_core_clks),
137+
.last_dt_core_clk = LAST_DT_CORE_CLK,
138+
.num_total_core_clks = MOD_CLK_BASE,
139+
140+
/* Module Clocks */
141+
.mod_clks = r9a09g047_mod_clks,
142+
.num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks),
143+
.num_hw_mod_clks = 28 * 16,
144+
145+
/* Resets */
146+
.resets = r9a09g047_resets,
147+
.num_resets = ARRAY_SIZE(r9a09g047_resets),
148+
149+
.num_mstop_bits = 208,
150+
};

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