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bebarinobebarino
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Merge tag 'renesas-clk-for-v6.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver udpates from Geert Uytterhoeven: - Add sound (SSI), remaining serial (SCIF), and ADC clocks, resets and power domains on Renesas RZ/G3S - Add system restart support on Renesas RZ/N1 - Add camera clocks and resets on Renesas RZ/V2H(P) - Add display clocks on Renesas R-Car V4M * tag 'renesas-clk-for-v6.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP clk: renesas: r8a779h0: Add display clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a06g032: Use BIT macro consistently clk: renesas: r9a06g032: Add restart handler clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSI clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init()
2 parents d3dcc98 + f962745 commit 39a72b4

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7 files changed

+180
-9
lines changed

7 files changed

+180
-9
lines changed

‎drivers/clk/renesas/r8a779h0-cpg-mssr.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
177177
DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2),
178178
DEF_MOD("csi40", 331, R8A779H0_CLK_CSI),
179179
DEF_MOD("csi41", 400, R8A779H0_CLK_CSI),
180+
DEF_MOD("dis0", 411, R8A779H0_CLK_VIOBUSD2),
181+
DEF_MOD("dsitxlink0", 415, R8A779H0_CLK_VIOBUSD2),
182+
DEF_MOD("fcpvd0", 508, R8A779H0_CLK_VIOBUSD2),
180183
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
181184
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
182185
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
@@ -225,6 +228,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
225228
DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO),
226229
DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO),
227230
DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO),
231+
DEF_MOD("vspd0", 830, R8A779H0_CLK_VIOBUSD2),
228232
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
229233
DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
230234
DEF_MOD("cmt1", 911, R8A779H0_CLK_R),

‎drivers/clk/renesas/r9a06g032-clocks.c

Lines changed: 28 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,15 +20,24 @@
2020
#include <linux/platform_device.h>
2121
#include <linux/pm_clock.h>
2222
#include <linux/pm_domain.h>
23+
#include <linux/reboot.h>
2324
#include <linux/slab.h>
2425
#include <linux/soc/renesas/r9a06g032-sysctrl.h>
2526
#include <linux/spinlock.h>
2627
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
2728

2829
#define R9A06G032_SYSCTRL_USB 0x00
29-
#define R9A06G032_SYSCTRL_USB_H2MODE (1<<1)
30+
#define R9A06G032_SYSCTRL_USB_H2MODE BIT(1)
3031
#define R9A06G032_SYSCTRL_DMAMUX 0xA0
3132

33+
#define R9A06G032_SYSCTRL_RSTEN 0x120
34+
#define R9A06G032_SYSCTRL_RSTEN_MRESET_EN BIT(0)
35+
#define R9A06G032_SYSCTRL_RSTCTRL 0x198
36+
/* These work for both reset registers */
37+
#define R9A06G032_SYSCTRL_SWRST BIT(6)
38+
#define R9A06G032_SYSCTRL_WDA7RST_1 BIT(2)
39+
#define R9A06G032_SYSCTRL_WDA7RST_0 BIT(1)
40+
3241
/**
3342
* struct regbit - describe one bit in a register
3443
* @reg: offset of register relative to base address,
@@ -1270,6 +1279,12 @@ static void r9a06g032_clocks_del_clk_provider(void *data)
12701279
of_clk_del_provider(data);
12711280
}
12721281

1282+
static int r9a06g032_restart_handler(struct sys_off_data *data)
1283+
{
1284+
writel(R9A06G032_SYSCTRL_SWRST, sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTCTRL);
1285+
return NOTIFY_DONE;
1286+
}
1287+
12731288
static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks)
12741289
{
12751290
struct device_node *usbf_np;
@@ -1324,6 +1339,18 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
13241339

13251340
r9a06g032_init_h2mode(clocks);
13261341

1342+
/* Clear potentially pending resets */
1343+
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
1344+
clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);
1345+
/* Allow software reset */
1346+
writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
1347+
clocks->reg + R9A06G032_SYSCTRL_RSTEN);
1348+
1349+
error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
1350+
r9a06g032_restart_handler, NULL);
1351+
if (error)
1352+
dev_warn(dev, "couldn't register restart handler (%d)\n", error);
1353+
13271354
for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
13281355
const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
13291356
const char *parent_name = d->source ?

‎drivers/clk/renesas/r9a08g045-cpg.c

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -187,6 +187,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
187187
DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
188188
DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),
189189
DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2),
190+
DEF_FIXED("TSU", R9A08G045_CLK_TSU, CLK_PLL2_DIV2, 1, 8),
190191
};
191192

192193
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
@@ -209,6 +210,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
209210
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
210211
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
211212
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
213+
DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0),
214+
DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1),
215+
DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2),
216+
DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3),
217+
DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4),
218+
DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5),
219+
DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6),
220+
DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7),
212221
DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0),
213222
DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1),
214223
DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2),
@@ -224,7 +233,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
224233
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
225234
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
226235
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
236+
DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1),
237+
DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2),
238+
DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3),
239+
DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4),
240+
DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5),
227241
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
242+
DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0),
243+
DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1),
228244
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
229245
};
230246

@@ -238,6 +254,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
238254
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
239255
DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
240256
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
257+
DEF_RST(R9A08G045_SSI0_RST_M2_REG, 0x870, 0),
258+
DEF_RST(R9A08G045_SSI1_RST_M2_REG, 0x870, 1),
259+
DEF_RST(R9A08G045_SSI2_RST_M2_REG, 0x870, 2),
260+
DEF_RST(R9A08G045_SSI3_RST_M2_REG, 0x870, 3),
241261
DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0),
242262
DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1),
243263
DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2),
@@ -249,9 +269,16 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
249269
DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
250270
DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
251271
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
272+
DEF_RST(R9A08G045_SCIF1_RST_SYSTEM_N, 0x884, 1),
273+
DEF_RST(R9A08G045_SCIF2_RST_SYSTEM_N, 0x884, 2),
274+
DEF_RST(R9A08G045_SCIF3_RST_SYSTEM_N, 0x884, 3),
275+
DEF_RST(R9A08G045_SCIF4_RST_SYSTEM_N, 0x884, 4),
276+
DEF_RST(R9A08G045_SCIF5_RST_SYSTEM_N, 0x884, 5),
252277
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
253278
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
254279
DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
280+
DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),
281+
DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),
255282
DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
256283
};
257284

@@ -286,6 +313,14 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
286313
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0),
287314
DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
288315
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0),
316+
DEF_PD("ssi0", R9A08G045_PD_SSI0,
317+
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0),
318+
DEF_PD("ssi1", R9A08G045_PD_SSI1,
319+
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0),
320+
DEF_PD("ssi2", R9A08G045_PD_SSI2,
321+
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0),
322+
DEF_PD("ssi3", R9A08G045_PD_SSI3,
323+
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0),
289324
DEF_PD("usb0", R9A08G045_PD_USB0,
290325
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0),
291326
DEF_PD("usb1", R9A08G045_PD_USB1,
@@ -306,6 +341,18 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
306341
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0),
307342
DEF_PD("scif0", R9A08G045_PD_SCIF0,
308343
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0),
344+
DEF_PD("scif1", R9A08G045_PD_SCIF1,
345+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)), 0),
346+
DEF_PD("scif2", R9A08G045_PD_SCIF2,
347+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)), 0),
348+
DEF_PD("scif3", R9A08G045_PD_SCIF3,
349+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)), 0),
350+
DEF_PD("scif4", R9A08G045_PD_SCIF4,
351+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0),
352+
DEF_PD("scif5", R9A08G045_PD_SCIF5,
353+
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0),
354+
DEF_PD("adc", R9A08G045_PD_ADC,
355+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0),
309356
DEF_PD("vbat", R9A08G045_PD_VBAT,
310357
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
311358
GENPD_FLAG_ALWAYS_ON),

‎drivers/clk/renesas/r9a09g057-cpg.c

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,21 @@ enum clk_ids {
2828
CLK_PLLCLN,
2929
CLK_PLLDTY,
3030
CLK_PLLCA55,
31+
CLK_PLLVDO,
3132

3233
/* Internal Core Clocks */
3334
CLK_PLLCM33_DIV16,
3435
CLK_PLLCLN_DIV2,
3536
CLK_PLLCLN_DIV8,
3637
CLK_PLLCLN_DIV16,
3738
CLK_PLLDTY_ACPU,
39+
CLK_PLLDTY_ACPU_DIV2,
3840
CLK_PLLDTY_ACPU_DIV4,
41+
CLK_PLLDTY_DIV16,
42+
CLK_PLLVDO_CRU0,
43+
CLK_PLLVDO_CRU1,
44+
CLK_PLLVDO_CRU2,
45+
CLK_PLLVDO_CRU3,
3946

4047
/* Module Clocks */
4148
MOD_CLK_BASE,
@@ -49,6 +56,12 @@ static const struct clk_div_table dtable_1_8[] = {
4956
{0, 0},
5057
};
5158

59+
static const struct clk_div_table dtable_2_4[] = {
60+
{0, 2},
61+
{1, 4},
62+
{0, 0},
63+
};
64+
5265
static const struct clk_div_table dtable_2_64[] = {
5366
{0, 2},
5467
{1, 4},
@@ -69,6 +82,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
6982
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
7083
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
7184
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
85+
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
7286

7387
/* Internal Core Clocks */
7488
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
@@ -78,7 +92,14 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
7892
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
7993

8094
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
95+
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
8196
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
97+
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
98+
99+
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
100+
DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
101+
DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
102+
DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
82103

83104
/* Core Clocks */
84105
DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -133,6 +154,18 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
133154
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),
134155
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),
135156
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
157+
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18),
158+
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19),
159+
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20),
160+
DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21),
161+
DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22),
162+
DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23),
163+
DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24),
164+
DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25),
165+
DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26),
166+
DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27),
167+
DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28),
168+
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29),
136169
};
137170

138171
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -162,6 +195,18 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
162195
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
163196
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
164197
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
198+
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
199+
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
200+
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
201+
DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
202+
DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
203+
DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
204+
DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
205+
DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
206+
DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
207+
DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
208+
DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
209+
DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
165210
};
166211

167212
const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {

‎drivers/clk/renesas/renesas-cpg-mssr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -979,7 +979,7 @@ static void __init cpg_mssr_reserved_exit(struct cpg_mssr_priv *priv)
979979
static int __init cpg_mssr_reserved_init(struct cpg_mssr_priv *priv,
980980
const struct cpg_mssr_info *info)
981981
{
982-
struct device_node *soc = of_find_node_by_path("/soc");
982+
struct device_node *soc __free(device_node) = of_find_node_by_path("/soc");
983983
struct device_node *node;
984984
uint32_t args[MAX_PHANDLE_ARGS];
985985
unsigned int *ids = NULL;

‎drivers/clk/renesas/rzv2h-cpg.c

Lines changed: 40 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,7 @@ struct pll_clk {
9898
*
9999
* @priv: CPG private data
100100
* @hw: handle between common and hardware-specific interfaces
101+
* @no_pm: flag to indicate PM is not supported
101102
* @on_index: register offset
102103
* @on_bit: ON/MON bit
103104
* @mon_index: monitor register offset
@@ -106,6 +107,7 @@ struct pll_clk {
106107
struct mod_clock {
107108
struct rzv2h_cpg_priv *priv;
108109
struct clk_hw hw;
110+
bool no_pm;
109111
u8 on_index;
110112
u8 on_bit;
111113
s8 mon_index;
@@ -541,6 +543,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
541543
clock->on_bit = mod->on_bit;
542544
clock->mon_index = mod->mon_index;
543545
clock->mon_bit = mod->mon_bit;
546+
clock->no_pm = mod->no_pm;
544547
clock->priv = priv;
545548
clock->hw.init = &init;
546549

@@ -668,17 +671,51 @@ struct rzv2h_cpg_pd {
668671
struct generic_pm_domain genpd;
669672
};
670673

674+
static bool rzv2h_cpg_is_pm_clk(struct rzv2h_cpg_pd *pd,
675+
const struct of_phandle_args *clkspec)
676+
{
677+
if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
678+
return false;
679+
680+
switch (clkspec->args[0]) {
681+
case CPG_MOD: {
682+
struct rzv2h_cpg_priv *priv = pd->priv;
683+
unsigned int id = clkspec->args[1];
684+
struct mod_clock *clock;
685+
686+
if (id >= priv->num_mod_clks)
687+
return false;
688+
689+
if (priv->clks[priv->num_core_clks + id] == ERR_PTR(-ENOENT))
690+
return false;
691+
692+
clock = to_mod_clock(__clk_get_hw(priv->clks[priv->num_core_clks + id]));
693+
694+
return !clock->no_pm;
695+
}
696+
697+
case CPG_CORE:
698+
default:
699+
return false;
700+
}
701+
}
702+
671703
static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
672704
{
705+
struct rzv2h_cpg_pd *pd = container_of(domain, struct rzv2h_cpg_pd, genpd);
673706
struct device_node *np = dev->of_node;
674707
struct of_phandle_args clkspec;
675708
bool once = true;
676709
struct clk *clk;
710+
unsigned int i;
677711
int error;
678-
int i = 0;
679712

680-
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
681-
&clkspec)) {
713+
for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) {
714+
if (!rzv2h_cpg_is_pm_clk(pd, &clkspec)) {
715+
of_node_put(clkspec.np);
716+
continue;
717+
}
718+
682719
if (once) {
683720
once = false;
684721
error = pm_clk_create(dev);
@@ -700,7 +737,6 @@ static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device
700737
error);
701738
goto fail_put;
702739
}
703-
i++;
704740
}
705741

706742
return 0;

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