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bebarinobebarino
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Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' into clk-next
* clk-socfpga: clk: socfpga: stratix10: Optimize local variables clk: socfpga: clk-pll: Optimize local variables * clk-sophgo: clk: sophgo: Add clock controller support for SG2044 SoC clk: sophgo: Add PLL clock controller support for SG2044 SoC dt-bindings: clock: sophgo: add clock controller for SG2044 dt-bindings: soc: sophgo: Add SG2044 top syscon device clk: sophgo: Add support for newly added precise compatible dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC * clk-thead: clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC dt-bindings: clock: thead: Add TH1520 VO clock controller * clk-samsung: clk: samsung: correct clock summary for hsi1 block clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition clk: samsung: exynosautov920: add cpucl1/2 clock support dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions clk: samsung: exynosautov920: add cpucl0 clock support dt-bindings: clock: exynosautov920: add cpucl0 clock definitions clk: samsung: Use samsung CCF common function
5 parents 7459da1 + 6bbc69e + a08f0ac + 29c98b1 + 3a4c538 commit 3e515fc

19 files changed

+3523
-73
lines changed

‎Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller
88

99
maintainers:
1010
- Sunyeal Hong <sunyeal.hong@samsung.com>
11+
- Shin Son <shin.son@samsung.com>
1112
- Chanwoo Choi <cw00.choi@samsung.com>
1213
- Krzysztof Kozlowski <krzk@kernel.org>
1314
- Sylwester Nawrocki <s.nawrocki@samsung.com>
@@ -32,6 +33,9 @@ properties:
3233
compatible:
3334
enum:
3435
- samsung,exynosautov920-cmu-top
36+
- samsung,exynosautov920-cmu-cpucl0
37+
- samsung,exynosautov920-cmu-cpucl1
38+
- samsung,exynosautov920-cmu-cpucl2
3539
- samsung,exynosautov920-cmu-peric0
3640
- samsung,exynosautov920-cmu-peric1
3741
- samsung,exynosautov920-cmu-misc
@@ -69,6 +73,71 @@ allOf:
6973
items:
7074
- const: oscclk
7175

76+
- if:
77+
properties:
78+
compatible:
79+
contains:
80+
enum:
81+
- samsung,exynosautov920-cmu-cpucl0
82+
83+
then:
84+
properties:
85+
clocks:
86+
items:
87+
- description: External reference clock (38.4 MHz)
88+
- description: CMU_CPUCL0 SWITCH clock (from CMU_TOP)
89+
- description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP)
90+
- description: CMU_CPUCL0 DBG clock (from CMU_TOP)
91+
92+
clock-names:
93+
items:
94+
- const: oscclk
95+
- const: switch
96+
- const: cluster
97+
- const: dbg
98+
99+
- if:
100+
properties:
101+
compatible:
102+
contains:
103+
enum:
104+
- samsung,exynosautov920-cmu-cpucl1
105+
106+
then:
107+
properties:
108+
clocks:
109+
items:
110+
- description: External reference clock (38.4 MHz)
111+
- description: CMU_CPUCL1 SWITCH clock (from CMU_TOP)
112+
- description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP)
113+
114+
clock-names:
115+
items:
116+
- const: oscclk
117+
- const: switch
118+
- const: cluster
119+
120+
- if:
121+
properties:
122+
compatible:
123+
contains:
124+
enum:
125+
- samsung,exynosautov920-cmu-cpucl2
126+
127+
then:
128+
properties:
129+
clocks:
130+
items:
131+
- description: External reference clock (38.4 MHz)
132+
- description: CMU_CPUCL2 SWITCH clock (from CMU_TOP)
133+
- description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP)
134+
135+
clock-names:
136+
items:
137+
- const: oscclk
138+
- const: switch
139+
- const: cluster
140+
72141
- if:
73142
properties:
74143
compatible:

‎Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,18 @@ maintainers:
1111

1212
properties:
1313
compatible:
14-
enum:
15-
- sophgo,cv1800-clk
16-
- sophgo,cv1810-clk
17-
- sophgo,sg2000-clk
14+
oneOf:
15+
- enum:
16+
- sophgo,cv1800b-clk
17+
- sophgo,cv1812h-clk
18+
- sophgo,sg2000-clk
19+
- items:
20+
- const: sophgo,sg2002-clk
21+
- const: sophgo,sg2000-clk
22+
- const: sophgo,cv1800-clk
23+
deprecated: true
24+
- const: sophgo,cv1810-clk
25+
deprecated: true
1826

1927
reg:
2028
maxItems: 1

‎Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml

Lines changed: 99 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,99 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Sophgo SG2044 Clock Controller
8+
9+
maintainers:
10+
- Inochi Amaoto <inochiama@gmail.com>
11+
12+
description: |
13+
The Sophgo SG2044 clock controller requires an external oscillator
14+
as input clock.
15+
16+
All available clocks are defined as preprocessor macros in
17+
include/dt-bindings/clock/sophgo,sg2044-clk.h
18+
19+
properties:
20+
compatible:
21+
const: sophgo,sg2044-clk
22+
23+
reg:
24+
maxItems: 1
25+
26+
clocks:
27+
items:
28+
- description: fpll0
29+
- description: fpll1
30+
- description: fpll2
31+
- description: dpll0
32+
- description: dpll1
33+
- description: dpll2
34+
- description: dpll3
35+
- description: dpll4
36+
- description: dpll5
37+
- description: dpll6
38+
- description: dpll7
39+
- description: mpll0
40+
- description: mpll1
41+
- description: mpll2
42+
- description: mpll3
43+
- description: mpll4
44+
- description: mpll5
45+
46+
clock-names:
47+
items:
48+
- const: fpll0
49+
- const: fpll1
50+
- const: fpll2
51+
- const: dpll0
52+
- const: dpll1
53+
- const: dpll2
54+
- const: dpll3
55+
- const: dpll4
56+
- const: dpll5
57+
- const: dpll6
58+
- const: dpll7
59+
- const: mpll0
60+
- const: mpll1
61+
- const: mpll2
62+
- const: mpll3
63+
- const: mpll4
64+
- const: mpll5
65+
66+
'#clock-cells':
67+
const: 1
68+
69+
required:
70+
- compatible
71+
- reg
72+
- clocks
73+
- '#clock-cells'
74+
75+
additionalProperties: false
76+
77+
examples:
78+
- |
79+
#include <dt-bindings/clock/sophgo,sg2044-pll.h>
80+
81+
clock-controller@50002000 {
82+
compatible = "sophgo,sg2044-clk";
83+
reg = <0x50002000 0x1000>;
84+
#clock-cells = <1>;
85+
clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
86+
<&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
87+
<&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
88+
<&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
89+
<&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
90+
<&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
91+
<&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
92+
<&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
93+
<&syscon CLK_MPLL5>;
94+
clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
95+
"dpll1", "dpll2", "dpll3", "dpll4",
96+
"dpll5", "dpll6", "dpll7", "mpll0",
97+
"mpll1", "mpll2", "mpll3", "mpll4",
98+
"mpll5";
99+
};

‎Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml

Lines changed: 14 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller
88

99
description: |
1010
The T-HEAD TH1520 AP sub-system clock controller configures the
11-
CPU, DPU, GMAC and TEE PLLs.
11+
CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures
12+
the clock gates for the HDMI, MIPI and the GPU.
1213
1314
SoC reference manual
1415
https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
@@ -20,14 +21,24 @@ maintainers:
2021

2122
properties:
2223
compatible:
23-
const: thead,th1520-clk-ap
24+
enum:
25+
- thead,th1520-clk-ap
26+
- thead,th1520-clk-vo
2427

2528
reg:
2629
maxItems: 1
2730

2831
clocks:
2932
items:
30-
- description: main oscillator (24MHz)
33+
- description: |
34+
One input clock:
35+
- For "thead,th1520-clk-ap": the clock input must be the 24 MHz
36+
main oscillator.
37+
- For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL,
38+
which is configured by the AP clock controller. According to the
39+
TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL
40+
(integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with
41+
a maximum FOUTVCO of 2376 MHz.
3142
3243
"#clock-cells":
3344
const: 1

‎Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-top-syscon.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Sophgo SG2044 SoC TOP system controller
8+
9+
maintainers:
10+
- Inochi Amaoto <inochiama@gmail.com>
11+
12+
description:
13+
The Sophgo SG2044 TOP system controller is a hardware block grouping
14+
multiple small functions, such as clocks and some other internal
15+
function.
16+
17+
properties:
18+
compatible:
19+
items:
20+
- const: sophgo,sg2044-top-syscon
21+
- const: syscon
22+
23+
reg:
24+
maxItems: 1
25+
26+
clocks:
27+
maxItems: 1
28+
29+
'#clock-cells':
30+
const: 1
31+
description:
32+
See <dt-bindings/clock/sophgo,sg2044-pll.h> for valid clock.
33+
34+
required:
35+
- compatible
36+
- reg
37+
- clocks
38+
- '#clock-cells'
39+
40+
additionalProperties: false
41+
42+
examples:
43+
- |
44+
syscon@50000000 {
45+
compatible = "sophgo,sg2044-top-syscon", "syscon";
46+
reg = <0x50000000 0x1000>;
47+
#clock-cells = <1>;
48+
clocks = <&osc>;
49+
};

‎drivers/clk/samsung/clk-exynos4.c

Lines changed: 42 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1269,6 +1269,45 @@ static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
12691269
CPUCLK_LAYOUT_E4210, e4412_armclk_d),
12701270
};
12711271

1272+
static const struct samsung_cmu_info cmu_info_exynos4 __initconst = {
1273+
.mux_clks = exynos4_mux_clks,
1274+
.nr_mux_clks = ARRAY_SIZE(exynos4_mux_clks),
1275+
.div_clks = exynos4_div_clks,
1276+
.nr_div_clks = ARRAY_SIZE(exynos4_div_clks),
1277+
.gate_clks = exynos4_gate_clks,
1278+
.nr_gate_clks = ARRAY_SIZE(exynos4_gate_clks),
1279+
.fixed_factor_clks = exynos4_fixed_factor_clks,
1280+
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4_fixed_factor_clks),
1281+
.fixed_clks = exynos4_fixed_rate_clks,
1282+
.nr_fixed_clks = ARRAY_SIZE(exynos4_fixed_rate_clks),
1283+
};
1284+
1285+
static const struct samsung_cmu_info cmu_info_exynos4210 __initconst = {
1286+
.mux_clks = exynos4210_mux_clks,
1287+
.nr_mux_clks = ARRAY_SIZE(exynos4210_mux_clks),
1288+
.div_clks = exynos4210_div_clks,
1289+
.nr_div_clks = ARRAY_SIZE(exynos4210_div_clks),
1290+
.gate_clks = exynos4210_gate_clks,
1291+
.nr_gate_clks = ARRAY_SIZE(exynos4210_gate_clks),
1292+
.fixed_factor_clks = exynos4210_fixed_factor_clks,
1293+
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4210_fixed_factor_clks),
1294+
.fixed_clks = exynos4210_fixed_rate_clks,
1295+
.nr_fixed_clks = ARRAY_SIZE(exynos4210_fixed_rate_clks),
1296+
.cpu_clks = exynos4210_cpu_clks,
1297+
.nr_cpu_clks = ARRAY_SIZE(exynos4210_cpu_clks),
1298+
};
1299+
1300+
static const struct samsung_cmu_info cmu_info_exynos4x12 __initconst = {
1301+
.mux_clks = exynos4x12_mux_clks,
1302+
.nr_mux_clks = ARRAY_SIZE(exynos4x12_mux_clks),
1303+
.div_clks = exynos4x12_div_clks,
1304+
.nr_div_clks = ARRAY_SIZE(exynos4x12_div_clks),
1305+
.gate_clks = exynos4x12_gate_clks,
1306+
.nr_gate_clks = ARRAY_SIZE(exynos4x12_gate_clks),
1307+
.fixed_factor_clks = exynos4x12_fixed_factor_clks,
1308+
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4x12_fixed_factor_clks),
1309+
};
1310+
12721311
/* register exynos4 clocks */
12731312
static void __init exynos4_clk_init(struct device_node *np,
12741313
enum exynos4_soc soc)
@@ -1322,41 +1361,12 @@ static void __init exynos4_clk_init(struct device_node *np,
13221361
ARRAY_SIZE(exynos4x12_plls));
13231362
}
13241363

1325-
samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1326-
ARRAY_SIZE(exynos4_fixed_rate_clks));
1327-
samsung_clk_register_mux(ctx, exynos4_mux_clks,
1328-
ARRAY_SIZE(exynos4_mux_clks));
1329-
samsung_clk_register_div(ctx, exynos4_div_clks,
1330-
ARRAY_SIZE(exynos4_div_clks));
1331-
samsung_clk_register_gate(ctx, exynos4_gate_clks,
1332-
ARRAY_SIZE(exynos4_gate_clks));
1333-
samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1334-
ARRAY_SIZE(exynos4_fixed_factor_clks));
1364+
samsung_cmu_register_clocks(ctx, &cmu_info_exynos4);
13351365

13361366
if (exynos4_soc == EXYNOS4210) {
1337-
samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1338-
ARRAY_SIZE(exynos4210_fixed_rate_clks));
1339-
samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1340-
ARRAY_SIZE(exynos4210_mux_clks));
1341-
samsung_clk_register_div(ctx, exynos4210_div_clks,
1342-
ARRAY_SIZE(exynos4210_div_clks));
1343-
samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1344-
ARRAY_SIZE(exynos4210_gate_clks));
1345-
samsung_clk_register_fixed_factor(ctx,
1346-
exynos4210_fixed_factor_clks,
1347-
ARRAY_SIZE(exynos4210_fixed_factor_clks));
1348-
samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
1349-
ARRAY_SIZE(exynos4210_cpu_clks));
1367+
samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210);
13501368
} else {
1351-
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1352-
ARRAY_SIZE(exynos4x12_mux_clks));
1353-
samsung_clk_register_div(ctx, exynos4x12_div_clks,
1354-
ARRAY_SIZE(exynos4x12_div_clks));
1355-
samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1356-
ARRAY_SIZE(exynos4x12_gate_clks));
1357-
samsung_clk_register_fixed_factor(ctx,
1358-
exynos4x12_fixed_factor_clks,
1359-
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1369+
samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12);
13601370
if (soc == EXYNOS4412)
13611371
samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
13621372
ARRAY_SIZE(exynos4412_cpu_clks));

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