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asm-generic: ticket-lock: Add separate ticket-lock.h
Add a separate ticket-lock.h to include multiple spinlock versions and select one at compile time or runtime. Reviewed-by: Leonardo Bras <leobras@redhat.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/linux-riscv/CAK8P3a2rnz9mQqhN6-e0CGUUv9rntRELFdxt_weiD7FxH7fkfQ@mail.gmail.com/ Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Andrea Parri <parri.andrea@gmail.com> Link: https://lore.kernel.org/r/20241103145153.105097-11-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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‎include/asm-generic/spinlock.h

Lines changed: 1 addition & 86 deletions
Original file line numberDiff line numberDiff line change
@@ -1,94 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* 'Generic' ticket-lock implementation.
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*
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* It relies on atomic_fetch_add() having well defined forward progress
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* guarantees under contention. If your architecture cannot provide this, stick
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* to a test-and-set lock.
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*
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* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
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* sub-word of the value. This is generally true for anything LL/SC although
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* you'd be hard pressed to find anything useful in architecture specifications
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* about this. If your architecture cannot do this you might be better off with
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* a test-and-set.
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*
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* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
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* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
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* a full fence after the spin to upgrade the otherwise-RCpc
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* atomic_cond_read_acquire().
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*
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* The implementation uses smp_cond_load_acquire() to spin, so if the
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* architecture has WFE like instructions to sleep instead of poll for word
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* modifications be sure to implement that (see ARM64 for example).
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*
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*/
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#ifndef __ASM_GENERIC_SPINLOCK_H
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#define __ASM_GENERIC_SPINLOCK_H
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#include <linux/atomic.h>
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#include <asm-generic/spinlock_types.h>
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static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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u32 val = atomic_fetch_add(1<<16, &lock->val);
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u16 ticket = val >> 16;
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if (ticket == (u16)val)
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return;
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/*
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* atomic_cond_read_acquire() is RCpc, but rather than defining a
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* custom cond_read_rcsc() here we just emit a full fence. We only
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* need the prior reads before subsequent writes ordering from
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* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
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* have no outstanding writes due to the atomic_fetch_add() the extra
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* orderings are free.
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*/
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atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL);
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smp_mb();
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}
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static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
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{
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u32 old = atomic_read(&lock->val);
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if ((old >> 16) != (old & 0xffff))
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return false;
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return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */
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}
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static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
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u32 val = atomic_read(&lock->val);
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smp_store_release(ptr, (u16)val + 1);
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}
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static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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u32 val = lock.val.counter;
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return ((val >> 16) == (val & 0xffff));
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}
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static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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arch_spinlock_t val = READ_ONCE(*lock);
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return !arch_spin_value_unlocked(val);
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}
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static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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u32 val = atomic_read(&lock->val);
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return (s16)((val >> 16) - (val & 0xffff)) > 1;
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}
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#include <asm-generic/ticket_spinlock.h>
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#include <asm/qrwlock.h>
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#endif /* __ASM_GENERIC_SPINLOCK_H */

‎include/asm-generic/ticket_spinlock.h

Lines changed: 103 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,103 @@
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/* SPDX-License-Identifier: GPL-2.0 */
2+
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/*
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* 'Generic' ticket-lock implementation.
5+
*
6+
* It relies on atomic_fetch_add() having well defined forward progress
7+
* guarantees under contention. If your architecture cannot provide this, stick
8+
* to a test-and-set lock.
9+
*
10+
* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
11+
* sub-word of the value. This is generally true for anything LL/SC although
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* you'd be hard pressed to find anything useful in architecture specifications
13+
* about this. If your architecture cannot do this you might be better off with
14+
* a test-and-set.
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*
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* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
17+
* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
18+
* a full fence after the spin to upgrade the otherwise-RCpc
19+
* atomic_cond_read_acquire().
20+
*
21+
* The implementation uses smp_cond_load_acquire() to spin, so if the
22+
* architecture has WFE like instructions to sleep instead of poll for word
23+
* modifications be sure to implement that (see ARM64 for example).
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*
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*/
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#ifndef __ASM_GENERIC_TICKET_SPINLOCK_H
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#define __ASM_GENERIC_TICKET_SPINLOCK_H
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#include <linux/atomic.h>
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#include <asm-generic/spinlock_types.h>
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static __always_inline void ticket_spin_lock(arch_spinlock_t *lock)
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{
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u32 val = atomic_fetch_add(1<<16, &lock->val);
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u16 ticket = val >> 16;
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if (ticket == (u16)val)
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return;
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/*
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* atomic_cond_read_acquire() is RCpc, but rather than defining a
43+
* custom cond_read_rcsc() here we just emit a full fence. We only
44+
* need the prior reads before subsequent writes ordering from
45+
* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
46+
* have no outstanding writes due to the atomic_fetch_add() the extra
47+
* orderings are free.
48+
*/
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atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL);
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smp_mb();
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}
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static __always_inline bool ticket_spin_trylock(arch_spinlock_t *lock)
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{
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u32 old = atomic_read(&lock->val);
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if ((old >> 16) != (old & 0xffff))
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return false;
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return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */
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}
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static __always_inline void ticket_spin_unlock(arch_spinlock_t *lock)
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{
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u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
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u32 val = atomic_read(&lock->val);
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68+
smp_store_release(ptr, (u16)val + 1);
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}
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static __always_inline int ticket_spin_value_unlocked(arch_spinlock_t lock)
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{
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u32 val = lock.val.counter;
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return ((val >> 16) == (val & 0xffff));
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}
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static __always_inline int ticket_spin_is_locked(arch_spinlock_t *lock)
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{
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arch_spinlock_t val = READ_ONCE(*lock);
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return !ticket_spin_value_unlocked(val);
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}
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static __always_inline int ticket_spin_is_contended(arch_spinlock_t *lock)
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{
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u32 val = atomic_read(&lock->val);
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return (s16)((val >> 16) - (val & 0xffff)) > 1;
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}
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/*
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* Remapping spinlock architecture specific functions to the corresponding
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* ticket spinlock functions.
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*/
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#define arch_spin_is_locked(l) ticket_spin_is_locked(l)
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#define arch_spin_is_contended(l) ticket_spin_is_contended(l)
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#define arch_spin_value_unlocked(l) ticket_spin_value_unlocked(l)
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#define arch_spin_lock(l) ticket_spin_lock(l)
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#define arch_spin_trylock(l) ticket_spin_trylock(l)
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#define arch_spin_unlock(l) ticket_spin_unlock(l)
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#endif /* __ASM_GENERIC_TICKET_SPINLOCK_H */

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