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bebarinobebarino
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Merge tag 'renesas-clk-for-v6.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas RZ/G3E * tag 'renesas-clk-for-v6.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a09g047: Add XSPI clock/reset clk: renesas: r9a09g047: Add support for xspi mux and divider dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks clk: renesas: Use str_on_off() helper
2 parents bef9652 + 28548f3 commit 1ffbdb7

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lines changed

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+52
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‎drivers/clk/renesas/r9a09g047-cpg.c

Lines changed: 38 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
enum clk_ids {
1818
/* Core Clock Outputs exported to DT */
19-
LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK,
19+
LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
2020

2121
/* External Input Clocks */
2222
CLK_AUDIO_EXTAL,
@@ -31,7 +31,14 @@ enum clk_ids {
3131
CLK_PLLVDO,
3232

3333
/* Internal Core Clocks */
34+
CLK_PLLCM33_DIV3,
35+
CLK_PLLCM33_DIV4,
36+
CLK_PLLCM33_DIV5,
3437
CLK_PLLCM33_DIV16,
38+
CLK_PLLCM33_GEAR,
39+
CLK_SMUX2_XSPI_CLK0,
40+
CLK_SMUX2_XSPI_CLK1,
41+
CLK_PLLCM33_XSPI,
3542
CLK_PLLCLN_DIV2,
3643
CLK_PLLCLN_DIV8,
3744
CLK_PLLCLN_DIV16,
@@ -61,6 +68,14 @@ static const struct clk_div_table dtable_2_4[] = {
6168
{0, 0},
6269
};
6370

71+
static const struct clk_div_table dtable_2_16[] = {
72+
{0, 2},
73+
{1, 4},
74+
{2, 8},
75+
{3, 16},
76+
{0, 0},
77+
};
78+
6479
static const struct clk_div_table dtable_2_64[] = {
6580
{0, 2},
6681
{1, 4},
@@ -70,6 +85,10 @@ static const struct clk_div_table dtable_2_64[] = {
7085
{0, 0},
7186
};
7287

88+
/* Mux clock tables */
89+
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
90+
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
91+
7392
static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
7493
/* External Clock Inputs */
7594
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -84,8 +103,17 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
84103
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
85104

86105
/* Internal Core Clocks */
106+
DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
107+
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
108+
DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
87109
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
88110

111+
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
112+
113+
DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
114+
DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
115+
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
116+
dtable_2_16),
89117
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
90118
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
91119
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
@@ -110,6 +138,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
110138
DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,
111139
CDDIV1_DIVCTL3, dtable_1_8),
112140
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
141+
DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
113142
};
114143

115144
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
@@ -155,6 +184,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
155184
BUS_MSTOP(10, BIT(14))),
156185
DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
157186
BUS_MSTOP(10, BIT(14))),
187+
DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
188+
BUS_MSTOP(4, BIT(5))),
189+
DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
190+
BUS_MSTOP(4, BIT(5))),
191+
DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
192+
BUS_MSTOP(4, BIT(5))),
158193
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
159194
BUS_MSTOP(8, BIT(2))),
160195
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
@@ -215,6 +250,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
215250
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
216251
DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */
217252
DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */
253+
DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
254+
DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
218255
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
219256
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
220257
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */

‎drivers/clk/renesas/renesas-cpg-mssr.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
#include <linux/psci.h>
2828
#include <linux/reset-controller.h>
2929
#include <linux/slab.h>
30+
#include <linux/string_choices.h>
3031

3132
#include <dt-bindings/clock/renesas-cpg-mssr.h>
3233

@@ -204,7 +205,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
204205
int error;
205206

206207
dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
207-
enable ? "ON" : "OFF");
208+
str_on_off(enable));
208209
spin_lock_irqsave(&priv->rmw_lock, flags);
209210

210211
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {

‎drivers/clk/renesas/rzg2l-cpg.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
#include <linux/pm_domain.h>
2828
#include <linux/reset-controller.h>
2929
#include <linux/slab.h>
30+
#include <linux/string_choices.h>
3031
#include <linux/units.h>
3132

3233
#include <dt-bindings/clock/renesas-cpg-mssr.h>
@@ -1217,7 +1218,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
12171218
}
12181219

12191220
dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", CLK_ON_R(reg), hw->clk,
1220-
enable ? "ON" : "OFF");
1221+
str_on_off(enable));
12211222

12221223
value = bitmask << 16;
12231224
if (enable)

‎drivers/clk/renesas/rzv2h-cpg.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,10 +93,12 @@ struct smuxed {
9393
.width = (_width), \
9494
})
9595

96+
#define CPG_SSEL1 (0x304)
9697
#define CPG_CDDIV0 (0x400)
9798
#define CPG_CDDIV1 (0x404)
9899
#define CPG_CDDIV3 (0x40C)
99100
#define CPG_CDDIV4 (0x410)
101+
#define CPG_CSDIV0 (0x500)
100102

101103
#define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
102104
#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
@@ -111,6 +113,11 @@ struct smuxed {
111113
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
112114
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
113115

116+
#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
117+
118+
#define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1)
119+
#define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1)
120+
114121
#define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
115122
#define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
116123
#define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \

‎include/dt-bindings/clock/renesas,r9a09g047-cpg.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,5 +17,8 @@
1717
#define R9A09G047_CM33_CLK0 6
1818
#define R9A09G047_CST_0_SWCLKTCK 7
1919
#define R9A09G047_IOTOP_0_SHCLK 8
20+
#define R9A09G047_SPI_CLK_SPI 9
21+
#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10
22+
#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11
2023

2124
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */

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