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Merge tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add GPU and USB2 clocks and resets on Renesas RZ/V2H(P) - Add support for the Renesas RZ/V2N (R9A09G056) SoC - Add GPU clocks and resets on Renesas RZ/G3E * tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (22 commits) clk: renesas: r9a09g057: Add clock and reset entries for USB2 dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable() clk: renesas: rzv2h: Support static dividers without RMW clk: renesas: rzv2h: Add macro for defining static dividers clk: renesas: rzv2h: Add support for static mux clocks clk: renesas: r9a09g047: Add clock and reset entries for GE3D clk: renesas: rzv2h: Fix a typo clk: renesas: rzv2h: Add support for RZ/V2N SoC clk: renesas: rzv2h: Sort compatible list based on SoC part number dt-bindings: pinctrl: renesas: Document RZ/V2N SoC dt-bindings: clock: renesas: Document RZ/V2N SoC CPG dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert() clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate() clk: renesas: r9a09g057: Add clock and reset entries for GE3D clk: renesas: rzv2h: Rename PLL field macros for consistency clk: renesas: rzv2h: Add support for enabling PLLs ...
2 parents 0af2f6b + 93f2878 commit bef9652

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‎Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,13 @@
44
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

7-
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
7+
title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
88

99
maintainers:
1010
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
1111

1212
description:
13-
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
13+
On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
1414
generation and control of clock signals for the IP modules, generation and
1515
control of resets, and control over booting, low power consumption and power
1616
supply domains.
@@ -19,6 +19,7 @@ properties:
1919
compatible:
2020
enum:
2121
- renesas,r9a09g047-cpg # RZ/G3E
22+
- renesas,r9a09g056-cpg # RZ/V2N
2223
- renesas,r9a09g057-cpg # RZ/V2H
2324

2425
reg:

‎Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ properties:
2727
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
2828
- renesas,r9a08g045-pinctrl # RZ/G3S
2929
- renesas,r9a09g047-pinctrl # RZ/G3E
30+
- renesas,r9a09g056-pinctrl # RZ/V2N
3031
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
3132

3233
- items:
@@ -145,6 +146,7 @@ allOf:
145146
contains:
146147
enum:
147148
- renesas,r9a09g047-pinctrl
149+
- renesas,r9a09g056-pinctrl
148150
- renesas,r9a09g057-pinctrl
149151
then:
150152
properties:

‎Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ properties:
2525
items:
2626
- enum:
2727
- renesas,r9a09g047-sys # RZ/G3E
28+
- renesas,r9a09g056-sys # RZ/V2N
2829
- renesas,r9a09g057-sys # RZ/V2H
2930

3031
reg:

‎Documentation/devicetree/bindings/soc/renesas/renesas.yaml

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -551,6 +551,21 @@ properties:
551551
- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
552552
- const: renesas,r9a09g047
553553

554+
- description: RZ/V2N (R9A09G056)
555+
items:
556+
- enum:
557+
- renesas,rzv2n-evk # RZ/V2N EVK (RTK0EF0186C03000BJ)
558+
- enum:
559+
- renesas,r9a09g056n41 # RZ/V2N
560+
- renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support
561+
- renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support
562+
- renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 support
563+
- renesas,r9a09g056n45 # RZ/V2N with cryptographic extension support
564+
- renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographic extension support
565+
- renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographic extension support
566+
- renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + cryptographic extension support
567+
- const: renesas,r9a09g056
568+
554569
- description: RZ/V2H(P) (R9A09G057)
555570
items:
556571
- enum:

‎drivers/clk/renesas/Kconfig

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ config CLK_RENESAS
4141
select CLK_R9A08G045 if ARCH_R9A08G045
4242
select CLK_R9A09G011 if ARCH_R9A09G011
4343
select CLK_R9A09G047 if ARCH_R9A09G047
44+
select CLK_R9A09G056 if ARCH_R9A09G056
4445
select CLK_R9A09G057 if ARCH_R9A09G057
4546
select CLK_SH73A0 if ARCH_SH73A0
4647

@@ -199,6 +200,10 @@ config CLK_R9A09G047
199200
bool "RZ/G3E clock support" if COMPILE_TEST
200201
select CLK_RZV2H
201202

203+
config CLK_R9A09G056
204+
bool "RZ/V2N clock support" if COMPILE_TEST
205+
select CLK_RZV2H
206+
202207
config CLK_R9A09G057
203208
bool "RZ/V2H(P) clock support" if COMPILE_TEST
204209
select CLK_RZV2H

‎drivers/clk/renesas/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
3838
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
3939
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
4040
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
41+
obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
4142
obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
4243
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
4344

‎drivers/clk/renesas/r9a09g047-cpg.c

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ enum clk_ids {
4141
CLK_PLLDTY_ACPU_DIV4,
4242
CLK_PLLDTY_DIV16,
4343
CLK_PLLVDO_CRU0,
44+
CLK_PLLVDO_GPU,
4445

4546
/* Module Clocks */
4647
MOD_CLK_BASE,
@@ -79,7 +80,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
7980
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
8081
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
8182
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
82-
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
83+
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
8384
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
8485

8586
/* Internal Core Clocks */
@@ -96,6 +97,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
9697
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
9798

9899
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
100+
DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
99101

100102
/* Core Clocks */
101103
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -183,6 +185,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
183185
BUS_MSTOP(9, BIT(4))),
184186
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
185187
BUS_MSTOP(9, BIT(4))),
188+
DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
189+
BUS_MSTOP(3, BIT(4))),
190+
DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
191+
BUS_MSTOP(3, BIT(4))),
192+
DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
193+
BUS_MSTOP(3, BIT(4))),
186194
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
187195
BUS_MSTOP(2, BIT(15))),
188196
};
@@ -213,6 +221,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
213221
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
214222
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
215223
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
224+
DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
225+
DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
226+
DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
216227
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
217228
};
218229

‎drivers/clk/renesas/r9a09g056-cpg.c

Lines changed: 152 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,152 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Renesas RZ/V2N CPG driver
4+
*
5+
* Copyright (C) 2025 Renesas Electronics Corp.
6+
*/
7+
8+
#include <linux/clk-provider.h>
9+
#include <linux/device.h>
10+
#include <linux/init.h>
11+
#include <linux/kernel.h>
12+
13+
#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
14+
15+
#include "rzv2h-cpg.h"
16+
17+
enum clk_ids {
18+
/* Core Clock Outputs exported to DT */
19+
LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I,
20+
21+
/* External Input Clocks */
22+
CLK_AUDIO_EXTAL,
23+
CLK_RTXIN,
24+
CLK_QEXTAL,
25+
26+
/* PLL Clocks */
27+
CLK_PLLCM33,
28+
CLK_PLLCLN,
29+
CLK_PLLDTY,
30+
CLK_PLLCA55,
31+
32+
/* Internal Core Clocks */
33+
CLK_PLLCM33_DIV16,
34+
CLK_PLLCLN_DIV2,
35+
CLK_PLLCLN_DIV8,
36+
CLK_PLLDTY_ACPU,
37+
CLK_PLLDTY_ACPU_DIV4,
38+
39+
/* Module Clocks */
40+
MOD_CLK_BASE,
41+
};
42+
43+
static const struct clk_div_table dtable_1_8[] = {
44+
{0, 1},
45+
{1, 2},
46+
{2, 4},
47+
{3, 8},
48+
{0, 0},
49+
};
50+
51+
static const struct clk_div_table dtable_2_64[] = {
52+
{0, 2},
53+
{1, 4},
54+
{2, 8},
55+
{3, 16},
56+
{4, 64},
57+
{0, 0},
58+
};
59+
60+
static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
61+
/* External Clock Inputs */
62+
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
63+
DEF_INPUT("rtxin", CLK_RTXIN),
64+
DEF_INPUT("qextal", CLK_QEXTAL),
65+
66+
/* PLL Clocks */
67+
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
68+
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
69+
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
70+
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
71+
72+
/* Internal Core Clocks */
73+
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
74+
75+
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
76+
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
77+
78+
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
79+
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
80+
81+
/* Core Clocks */
82+
DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
83+
DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55,
84+
CDDIV1_DIVCTL0, dtable_1_8),
85+
DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55,
86+
CDDIV1_DIVCTL1, dtable_1_8),
87+
DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55,
88+
CDDIV1_DIVCTL2, dtable_1_8),
89+
DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
90+
CDDIV1_DIVCTL3, dtable_1_8),
91+
DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
92+
};
93+
94+
static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
95+
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
96+
BUS_MSTOP(3, BIT(5))),
97+
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
98+
BUS_MSTOP(3, BIT(14))),
99+
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
100+
BUS_MSTOP(8, BIT(2))),
101+
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
102+
BUS_MSTOP(8, BIT(2))),
103+
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
104+
BUS_MSTOP(8, BIT(2))),
105+
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
106+
BUS_MSTOP(8, BIT(2))),
107+
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
108+
BUS_MSTOP(8, BIT(3))),
109+
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
110+
BUS_MSTOP(8, BIT(3))),
111+
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
112+
BUS_MSTOP(8, BIT(3))),
113+
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
114+
BUS_MSTOP(8, BIT(3))),
115+
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
116+
BUS_MSTOP(8, BIT(4))),
117+
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
118+
BUS_MSTOP(8, BIT(4))),
119+
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
120+
BUS_MSTOP(8, BIT(4))),
121+
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
122+
BUS_MSTOP(8, BIT(4))),
123+
};
124+
125+
static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
126+
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
127+
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
128+
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
129+
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
130+
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
131+
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
132+
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
133+
};
134+
135+
const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {
136+
/* Core Clocks */
137+
.core_clks = r9a09g056_core_clks,
138+
.num_core_clks = ARRAY_SIZE(r9a09g056_core_clks),
139+
.last_dt_core_clk = LAST_DT_CORE_CLK,
140+
.num_total_core_clks = MOD_CLK_BASE,
141+
142+
/* Module Clocks */
143+
.mod_clks = r9a09g056_mod_clks,
144+
.num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks),
145+
.num_hw_mod_clks = 25 * 16,
146+
147+
/* Resets */
148+
.resets = r9a09g056_resets,
149+
.num_resets = ARRAY_SIZE(r9a09g056_resets),
150+
151+
.num_mstop_bits = 192,
152+
};

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