Allow for fetching measurements while matching LogicPortPins

Author: hdoordt

cli/src/main.rs

@@ -1,15 +1,15 @@
 use anyhow::Result;
 use clap::Parser;
 use ppk2::{
-    types::{DevicePower, MeasurementMode, SourceVoltage},
+    types::{DevicePower, MeasurementMode, SourceVoltage, LogicPortPins, Level},
     Ppk2, try_find_ppk2_port,
 };
 
 use std::{
     sync::mpsc::RecvTimeoutError,
     time::{Duration, Instant},
 };
-use tracing::{debug, error, info, Level};
+use tracing::{debug, error, info, Level as LogLevel};
 use tracing_subscriber::FmtSubscriber;
 
 #[derive(Parser)]
@@ -50,7 +50,7 @@ struct Args {
     mode: MeasurementMode,
 
     #[clap(env, short = 'l', long, help = "The log level", default_value = "info")]
-    log_level: Level,
+    log_level: LogLevel,
 
     #[clap(
         env,
@@ -79,7 +79,10 @@ fn main() -> Result<()> {
 
     ppk2.set_source_voltage(args.voltage)?;
     ppk2.set_device_power(args.power)?;
-    let (rx, kill) = ppk2.start_measuring(args.sps)?;
+    let mut levels = [Level::Either; 8];
+    levels[0] = Level::Low;
+    let pins = LogicPortPins::with_levels(levels);
+    let (rx, kill) = ppk2.start_measuring_while_matches(pins, args.sps)?;
 
     let mut kill = Some(kill);
 

ppk2/src/lib.rs

@@ -14,7 +14,7 @@ use std::{
     time::Duration,
 };
 use thiserror::Error;
-use types::{DevicePower, MeasurementMode, Metadata, SourceVoltage};
+use types::{DevicePower, LogicPortPins, MeasurementMode, Metadata, SourceVoltage};
 
 use crate::cmd::Command;
 
@@ -110,10 +110,14 @@ impl Ppk2 {
     /// - [Receiver] of [measurement::Result], and
     /// - A closure that can be called to stop the measurement parsing pipeline and return the
     /// device.
-    pub fn start_measuring(
+    pub fn start_measuring_while_matches(
         mut self,
+        pins: LogicPortPins,
         sps: usize,
-    ) -> Result<(Receiver<measurement::Measurement>, impl FnOnce() -> Result<Self>)> {
+    ) -> Result<(
+        Receiver<measurement::Measurement>,
+        impl FnOnce() -> Result<Self>,
+    )> {
         // Stuff needed to communicate with the main thread
         // ready allows main thread to signal worker when serial input buf is cleared.
         let ready = Arc::new((Mutex::new(false), Condvar::new()));
@@ -141,6 +145,7 @@ impl Ppk2 {
                 let mut buf = [0u8; 1024];
                 let mut measurement_buf = VecDeque::with_capacity(SPS_MAX);
                 let mut missed = 0;
+                let mut did_get_matches = false;
                 loop {
                     // Check whether the main thread has signaled
                     // us to stop
@@ -155,8 +160,18 @@ impl Ppk2 {
                     missed += accumulator.feed_into(&buf[..n], &mut measurement_buf);
                     let len = measurement_buf.len();
                     if len >= SPS_MAX / sps {
-                        let measurement = measurement_buf.drain(..).combine(missed);                        
-                        meas_tx.send(measurement)?;
+                        let measurement = measurement_buf.drain(..).combine_matching(missed, pins);
+                        match measurement {
+                            Some(m) => {
+                                meas_tx.send(m)?;
+                                did_get_matches = true;
+                            }
+                            None if did_get_matches => {
+                                break Ok(());
+                            },
+                            _ => {/* No matching measurements yet, wait for them to come up */},
+                        }
+
                         missed = 0;
                     }
                 }
@@ -210,4 +225,4 @@ pub fn try_find_ppk2_port() -> Result<String> {
         })
         .ok_or(Error::Ppk2NotFound)?
         .port_name)
-}
+}

ppk2/src/measurement.rs

@@ -2,7 +2,7 @@
 
 use std::collections::VecDeque;
 
-use crate::types::{Metadata, LogicPortPins};
+use crate::types::{LogicPortPins, Metadata};
 
 const ADC_MULTIPLIER: f32 = 1.8 / 163840.;
 const SPIKE_FILTER_ALPHA: f32 = 0.18;
@@ -97,7 +97,10 @@ impl MeasurementAccumulator {
                 self.state.expected_counter.replace(counter);
             }
 
-            buf.push_back(Measurement { micro_amps, pins: bits })
+            buf.push_back(Measurement {
+                micro_amps,
+                pins: bits,
+            })
         }
         self.buf.drain(..end);
         samples_missed
@@ -164,12 +167,15 @@ fn get_adc_result(
 
 /// Extension trait for VecDeque<Measurement>
 pub trait MeasurementIterExt {
-    /// Combine items into a single [Measurement]. T
-    fn combine(self, missed: usize) -> Measurement;
+    /// Combine items into a single [Measurement], if there are items.
+    fn combine(self, missed: usize) -> Option<Measurement>;
+
+    /// Combine items with matching logic port pins into a single [Measurement], if any.
+    fn combine_matching(self, missed: usize, matching_pins: LogicPortPins) -> Option<Measurement>;
 }
 
 impl<I: Iterator<Item = Measurement>> MeasurementIterExt for I {
-    fn combine(self, missed: usize) -> Measurement {
+    fn combine(self, missed: usize) -> Option<Measurement> {
         let mut pin_high_count = [0usize; 8];
         let mut count = 0;
         let mut sum = 0f32;
@@ -180,10 +186,15 @@ impl<I: Iterator<Item = Measurement>> MeasurementIterExt for I {
                 .inner()
                 .iter()
                 .enumerate()
-                .filter(|(_, &p)| p)
+                .filter(|(_, &p)| p.is_high())
                 .for_each(|(i, _)| pin_high_count[i] += 1);
         });
 
+        if count == 0 {
+            // No measurements
+            return None;
+        }
+
         let mut pins = [false; 8];
         pin_high_count
             .into_iter()
@@ -192,10 +203,21 @@ impl<I: Iterator<Item = Measurement>> MeasurementIterExt for I {
             .for_each(|(i, _)| pins[i] = true);
         let avg = sum / (count - missed) as f32;
 
-        Measurement {
+        Some(Measurement {
             micro_amps: avg,
             pins: pins.into(),
-        }
+        })
+    }
+
+    fn combine_matching(self, missed: usize, matching_pins: LogicPortPins) -> Option<Measurement> {
+        let iter = self.filter(|m| {
+            m.pins
+                .inner()
+                .iter()
+                .enumerate()
+                .all(|(i, l)| l.matches(matching_pins.inner()[i]))
+        });
+        iter.combine(missed)
     }
 }
 

ppk2/src/types.rs

@@ -136,17 +136,65 @@ impl FromStr for DevicePower {
     }
 }
 
+/// Logic level for logic port pins
+#[derive(Debug, Clone, Copy)]
+pub enum Level {
+    /// Low level
+    Low,
+    /// High level
+    High,
+    /// Either level. Used for matching only.
+    Either,
+}
+
+impl From<bool> for Level {
+    fn from(level: bool) -> Self {
+        use Level::*;
+        match level {
+            true => High,
+            false => Low,
+        }
+    }
+}
+
+impl Level {
+    /// Check whether the level is high.
+    pub fn is_high(&self) -> bool {
+        matches!(self, Level::High)
+    }
+
+    /// Check whether the level is low.
+    pub fn is_low(&self) -> bool {
+        matches!(self, Level::Low)
+    }
+
+    /// Check whether the [Level] matches another.
+    pub fn matches(&self, other: Level) -> bool {
+        match (self, other) {
+            (_, Level::Either) => true,
+            (Level::Either, _) => true,
+            (Level::Low, Level::Low) => true,
+            (Level::High, Level::High) => true,
+            _ => false,
+        }
+    }
+}
+
 /// Logic port state
 #[derive(Debug, Clone, Copy)]
 pub struct LogicPortPins {
-    pins: [bool; 8],
+    pin_levels: [Level; 8],
 }
 
 impl LogicPortPins {
+    /// Set up a new [LogicPortPins] with given [Level]s
+    pub fn with_levels(pin_levels: [Level; 8]) -> Self {
+        Self { pin_levels }
+    }
+
     /// Check whether a pin level is high
     pub fn pin_is_high(&self, pin: usize) -> bool {
-        assert!(pin < 8);
-        self.pins[pin]
+        self.pin_levels[pin].is_high()
     }
 
     /// Check whether a pin level is low
@@ -155,14 +203,18 @@ impl LogicPortPins {
     }
 
     /// Get a reference to the internal pin array
-    pub fn inner(&self) -> &[bool; 8] {
-        &self.pins
+    pub fn inner(&self) -> &[Level; 8] {
+        &self.pin_levels
     }
 }
 
 impl From<[bool; 8]> for LogicPortPins {
-    fn from(pins: [bool; 8]) -> Self {
-        Self { pins }
+    fn from(pin_bools: [bool; 8]) -> Self {
+        let mut pins = [Level::Low; 8];
+        pin_bools.iter().enumerate().for_each(|(i, &p)| {
+            pins[i] = p.into();
+        });
+        Self { pin_levels: pins }
     }
 }