Fast Multiplication algorithm in SystemVerilog by using 4 to 2 compressors combined with Half adders and CSA (Carry Sum Adders)
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fix cin bug on removal of '{default:'0} for synthesis error
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Now to make 16 bit, 32 bit and 64 bit : )
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but first need to make a signed 8 bit multiplier
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- making the 8 bit tree took me over 24 hours of work lmaoo bc stupid bugs and complicated tree
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- on the plus side, the code is much more readable than other trees I have seen online
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Of several 4:2 compression techniques, this should be the most optimal routing to ensure fastest result, however, I acknowledge that modern Synthesis tools may be better at optimization
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at end of multiplication tree, just use CPA (Carry Propogate Adder) to get final results