Hi, I am a chip design enthusiast!

Skills Overview

Bash Shell Scripting

I have proficiency in Bash shell scripting for automation and task automation purposes.

Vim-based Document Editing

I am skilled in using Vim for efficient text editing and manipulation.

Version Control Using Git

I am experienced in using Git for version control, including branching, merging, and collaborating with others on projects.

Command-line Environment

I am comfortable working in a command-line environment and executing various tasks efficiently.

Makefiles

I have knowledge of creating and using Makefiles for building complex projects with dependencies.

C Memory Management

I am proficient in memory management techniques in the C programming language.

C Language GNU Debugger

I have experience using the GNU debugger (GDB) for debugging C programs.

C Inline Function and Inline Assembly

I am familiar with inline function and inline assembly usage in the C programming language for optimization purposes.

Introduction to RISC-V 32-bit ISA and Assembly Programming

I have a basic understanding of RISC-V 32-bit Instruction Set Architecture (ISA) and assembly programming concepts.

Verilog Combinational and Sequential Designs

I am skilled in designing combinational and sequential circuits using Verilog.

FPGA Design with Zynq SoCs, Spartan 6, Nexus 3

I have hands-on experience in FPGA designs, specializing in Zynq SoCs (7010, 7020), Spartan 6, and Nexus 3.

Design and Development of Military-Standard Software-Defined Radios

I have been involved in the design and development of military-standard software-defined radios, integrating various modules such as ADC/DAC, PLL, EEPROM, RTC IC integration, SPI, I2C, UART, and RF Front End on FPGA.

Linux and PetaLinux for Embedded Systems Development

I am proficient in working with Linux and PetaLinux for embedded systems development, focusing on crafting device drivers for ARM Cortex-A9 of Zynq SoC within the Petalinux root system.

Design and Implementation of Intellectual Properties (IPs) Using HLS, Verilog/VHDL

I have experience in designing and implementing Intellectual Properties (IPs) using High-Level Synthesis (HLS), Verilog, and VHDL.

Basic Static Timing Analysis (STA), Area, Power, and Design Optimization Using Xilinx Vivado Tools

I am skilled in performing basic Static Timing Analysis (STA), and optimizing designs for Area, Power, and Performance using Xilinx Vivado tools for FPGA development.

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Feel free to reach out to me if you have any questions or would like to collaborate on projects related to these areas.