Leakage Power Reduction Techniques in Deep Submicron Technologies.

The Sleepy Keeper Technique (SKT) is a low-power VLSI design method that reduces leakage power while retaining circuit state. It uses sleep transistors (PMOS and NMOS) to disconnect the circuit from power (Vdd) and ground (GND) during standby mode, minimizing leakage current. A small keeper transistor is placed parallel to the sleep transistor to maintain a weak connection, ensuring that logic states are preserved even when the circuit is in sleep mode. This technique provides better leakage reduction than the Sleepy Stack method while avoiding data loss. However, it increases circuit area due to additional transistors.

Softwares Used

1. Vivado
2. DSCH (Digital Schematic)
3. Microwind

1. Sleepy Keeper Concept NAND Logic

A NAND gate (NOT AND) is a fundamental digital logic gate that produces a LOW (0) output only when all its inputs are HIGH (1); otherwise, it outputs HIGH (1). It is considered a universal gate because it can be used to implement any other logic gate, including AND, OR, and NOT gates.

Schematic in DSCH

Layout Design in Microwind Sleepy Keeper concept NAND Transistor Level Layout diagram designed in microwind software.

Logic Timing Diagram

2. Sleepy Keeper Half Adder Circuit

A Half Adder is a fundamental digital circuit used for adding two single-bit binary numbers. It has two inputs and produces two outputs: Sum and Carry. The Sum output represents the result of the addition, while the Carry output indicates if there is a carry to the next higher bit. Since a half adder does not account for carry input from a previous stage, it is mainly used in basic arithmetic operations where carry propagation is not required.

Schematic in DSCH

Layout Design

Logic Timing Diagram

3. Sleepy Keeper NOR Transistor Level Circuit

A NOR gate (NOT OR) is a digital logic gate that produces a HIGH (1) output only when all its inputs are LOW (0); otherwise, it outputs LOW (0). It is a universal gate, meaning it can be used to construct any other logic gate, including AND, OR, and NOT. NOR gates are commonly used in digital circuits for logic minimization and designing combinational and sequential circuits.

Schematic in DSCH

Layout Design

Logic Timing Diagram