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Promote design partially routed and timing failures to fatal errors
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hdk/cl/developer_designs/cl_firesim/build/scripts/create_dcp_from_cl.tcl

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@@ -144,6 +144,10 @@ set_msg_config -id {DRC CKLD-2} -suppress
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set_msg_config -id {DRC REQP-1853} -suppress
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set_msg_config -id {Timing 38-436} -suppress
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# Promote the following critical warnings to errors to prevent AGFI generation
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# Design not completely routed
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set_msg_config -id {Route 35-1} -new_severity "ERROR"
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# Check that an email address has been set, else unset notify_via_sns
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if {[string compare $notify_via_sns "1"] == 0} {
@@ -313,6 +317,12 @@ if {$implement} {
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-route optimization";
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impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl
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}
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# Check if slack has improved after physopt.
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set SLACK [get_property SLACK [get_timing_paths]]
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if {$SLACK < 0} {
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puts "\nFATAL: Design did not meet timing requirements. Terminating.";
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exit 3
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}
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##############################
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# Final Implmentation Steps

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