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davidbiancolindavidbiancolin
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Remove unneeded connections between DRAM and F1Shim
1 parent f7915f6 commit e292b3d

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+1
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‎hdk/cl/developer_designs/cl_firesim/design/cl_firesim.sv

Lines changed: 1 addition & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1089,23 +1089,18 @@ wire fsimtop_s_3_axi_rready;
10891089
.io_slave_0_aw_bits_cache(fsimtop_s_0_axi_awcache), // not available on DDR IF
10901090
.io_slave_0_aw_bits_prot(fsimtop_s_0_axi_awprot), // not available on DDR IF
10911091
.io_slave_0_aw_bits_qos(fsimtop_s_0_axi_awqos), // not available on DDR IF
1092-
.io_slave_0_aw_bits_region(fsimtop_s_0_axi_awregion), // not available on DDR IF
10931092
.io_slave_0_aw_bits_id(fsimtop_s_0_axi_awid),
1094-
.io_slave_0_aw_bits_user(), // not available on DDR IF
10951093

10961094
.io_slave_0_w_ready(fsimtop_s_0_axi_wready),
10971095
.io_slave_0_w_valid(fsimtop_s_0_axi_wvalid),
10981096
.io_slave_0_w_bits_data(fsimtop_s_0_axi_wdata),
10991097
.io_slave_0_w_bits_last(fsimtop_s_0_axi_wlast),
1100-
.io_slave_0_w_bits_id(),
11011098
.io_slave_0_w_bits_strb(fsimtop_s_0_axi_wstrb),
1102-
.io_slave_0_w_bits_user(), // not available on DDR IF
11031099

11041100
.io_slave_0_b_ready(fsimtop_s_0_axi_bready),
11051101
.io_slave_0_b_valid(fsimtop_s_0_axi_bvalid),
11061102
.io_slave_0_b_bits_resp(fsimtop_s_0_axi_bresp),
11071103
.io_slave_0_b_bits_id(fsimtop_s_0_axi_bid),
1108-
.io_slave_0_b_bits_user(1'b0), // TODO check this
11091104

11101105
.io_slave_0_ar_ready(fsimtop_s_0_axi_arready),
11111106
.io_slave_0_ar_valid(fsimtop_s_0_axi_arvalid),
@@ -1117,17 +1112,14 @@ wire fsimtop_s_3_axi_rready;
11171112
.io_slave_0_ar_bits_cache(fsimtop_s_0_axi_arcache), // not available on DDR IF
11181113
.io_slave_0_ar_bits_prot(fsimtop_s_0_axi_arprot), // not available on DDR IF
11191114
.io_slave_0_ar_bits_qos(fsimtop_s_0_axi_arqos), // not available on DDR IF
1120-
.io_slave_0_ar_bits_region(fsimtop_s_0_axi_arregion), // not available on DDR IF
11211115
.io_slave_0_ar_bits_id(fsimtop_s_0_axi_arid), // not available on DDR IF
1122-
.io_slave_0_ar_bits_user(), // not available on DDR IF
11231116

11241117
.io_slave_0_r_ready(fsimtop_s_0_axi_rready),
11251118
.io_slave_0_r_valid(fsimtop_s_0_axi_rvalid),
11261119
.io_slave_0_r_bits_resp(fsimtop_s_0_axi_rresp),
11271120
.io_slave_0_r_bits_data(fsimtop_s_0_axi_rdata),
11281121
.io_slave_0_r_bits_last(fsimtop_s_0_axi_rlast),
11291122
.io_slave_0_r_bits_id(fsimtop_s_0_axi_rid),
1130-
.io_slave_0_r_bits_user(1'b0), // TODO check this
11311123

11321124
.io_slave_1_aw_ready(fsimtop_s_1_axi_awready),
11331125
.io_slave_1_aw_valid(fsimtop_s_1_axi_awvalid),
@@ -1139,23 +1131,18 @@ wire fsimtop_s_3_axi_rready;
11391131
.io_slave_1_aw_bits_cache(fsimtop_s_1_axi_awcache), // not available on DDR IF
11401132
.io_slave_1_aw_bits_prot(fsimtop_s_1_axi_awprot), // not available on DDR IF
11411133
.io_slave_1_aw_bits_qos(fsimtop_s_1_axi_awqos), // not available on DDR IF
1142-
.io_slave_1_aw_bits_region(fsimtop_s_1_axi_awregion), // not available on DDR IF
11431134
.io_slave_1_aw_bits_id(fsimtop_s_1_axi_awid),
1144-
.io_slave_1_aw_bits_user(), // not available on DDR IF
11451135

11461136
.io_slave_1_w_ready(fsimtop_s_1_axi_wready),
11471137
.io_slave_1_w_valid(fsimtop_s_1_axi_wvalid),
11481138
.io_slave_1_w_bits_data(fsimtop_s_1_axi_wdata),
11491139
.io_slave_1_w_bits_last(fsimtop_s_1_axi_wlast),
1150-
.io_slave_1_w_bits_id(),
11511140
.io_slave_1_w_bits_strb(fsimtop_s_1_axi_wstrb),
1152-
.io_slave_1_w_bits_user(), // not available on DDR IF
11531141

11541142
.io_slave_1_b_ready(fsimtop_s_1_axi_bready),
11551143
.io_slave_1_b_valid(fsimtop_s_1_axi_bvalid),
11561144
.io_slave_1_b_bits_resp(fsimtop_s_1_axi_bresp),
11571145
.io_slave_1_b_bits_id(fsimtop_s_1_axi_bid),
1158-
.io_slave_1_b_bits_user(1'b0), // TODO check this
11591146

11601147
.io_slave_1_ar_ready(fsimtop_s_1_axi_arready),
11611148
.io_slave_1_ar_valid(fsimtop_s_1_axi_arvalid),
@@ -1167,18 +1154,14 @@ wire fsimtop_s_3_axi_rready;
11671154
.io_slave_1_ar_bits_cache(fsimtop_s_1_axi_arcache), // not available on DDR IF
11681155
.io_slave_1_ar_bits_prot(fsimtop_s_1_axi_arprot), // not available on DDR IF
11691156
.io_slave_1_ar_bits_qos(fsimtop_s_1_axi_arqos), // not available on DDR IF
1170-
.io_slave_1_ar_bits_region(fsimtop_s_1_axi_arregion), // not available on DDR IF
11711157
.io_slave_1_ar_bits_id(fsimtop_s_1_axi_arid), // not available on DDR IF
1172-
.io_slave_1_ar_bits_user(), // not available on DDR IF
11731158

11741159
.io_slave_1_r_ready(fsimtop_s_1_axi_rready),
11751160
.io_slave_1_r_valid(fsimtop_s_1_axi_rvalid),
11761161
.io_slave_1_r_bits_resp(fsimtop_s_1_axi_rresp),
11771162
.io_slave_1_r_bits_data(fsimtop_s_1_axi_rdata),
11781163
.io_slave_1_r_bits_last(fsimtop_s_1_axi_rlast),
11791164
.io_slave_1_r_bits_id(fsimtop_s_1_axi_rid),
1180-
.io_slave_1_r_bits_user(1'b0), // TODO check this
1181-
11821165

11831166
.io_slave_2_aw_ready(fsimtop_s_2_axi_awready),
11841167
.io_slave_2_aw_valid(fsimtop_s_2_axi_awvalid),
@@ -1190,23 +1173,18 @@ wire fsimtop_s_3_axi_rready;
11901173
.io_slave_2_aw_bits_cache(fsimtop_s_2_axi_awcache), // not available on DDR IF
11911174
.io_slave_2_aw_bits_prot(fsimtop_s_2_axi_awprot), // not available on DDR IF
11921175
.io_slave_2_aw_bits_qos(fsimtop_s_2_axi_awqos), // not available on DDR IF
1193-
.io_slave_2_aw_bits_region(fsimtop_s_2_axi_awregion), // not available on DDR IF
11941176
.io_slave_2_aw_bits_id(fsimtop_s_2_axi_awid),
1195-
.io_slave_2_aw_bits_user(), // not available on DDR IF
11961177

11971178
.io_slave_2_w_ready(fsimtop_s_2_axi_wready),
11981179
.io_slave_2_w_valid(fsimtop_s_2_axi_wvalid),
11991180
.io_slave_2_w_bits_data(fsimtop_s_2_axi_wdata),
12001181
.io_slave_2_w_bits_last(fsimtop_s_2_axi_wlast),
1201-
.io_slave_2_w_bits_id(),
12021182
.io_slave_2_w_bits_strb(fsimtop_s_2_axi_wstrb),
1203-
.io_slave_2_w_bits_user(), // not available on DDR IF
12041183

12051184
.io_slave_2_b_ready(fsimtop_s_2_axi_bready),
12061185
.io_slave_2_b_valid(fsimtop_s_2_axi_bvalid),
12071186
.io_slave_2_b_bits_resp(fsimtop_s_2_axi_bresp),
12081187
.io_slave_2_b_bits_id(fsimtop_s_2_axi_bid),
1209-
.io_slave_2_b_bits_user(1'b0), // TODO check this
12101188

12111189
.io_slave_2_ar_ready(fsimtop_s_2_axi_arready),
12121190
.io_slave_2_ar_valid(fsimtop_s_2_axi_arvalid),
@@ -1218,17 +1196,14 @@ wire fsimtop_s_3_axi_rready;
12181196
.io_slave_2_ar_bits_cache(fsimtop_s_2_axi_arcache), // not available on DDR IF
12191197
.io_slave_2_ar_bits_prot(fsimtop_s_2_axi_arprot), // not available on DDR IF
12201198
.io_slave_2_ar_bits_qos(fsimtop_s_2_axi_arqos), // not available on DDR IF
1221-
.io_slave_2_ar_bits_region(fsimtop_s_2_axi_arregion), // not available on DDR IF
12221199
.io_slave_2_ar_bits_id(fsimtop_s_2_axi_arid), // not available on DDR IF
1223-
.io_slave_2_ar_bits_user(), // not available on DDR IF
12241200

12251201
.io_slave_2_r_ready(fsimtop_s_2_axi_rready),
12261202
.io_slave_2_r_valid(fsimtop_s_2_axi_rvalid),
12271203
.io_slave_2_r_bits_resp(fsimtop_s_2_axi_rresp),
12281204
.io_slave_2_r_bits_data(fsimtop_s_2_axi_rdata),
12291205
.io_slave_2_r_bits_last(fsimtop_s_2_axi_rlast),
12301206
.io_slave_2_r_bits_id(fsimtop_s_2_axi_rid),
1231-
.io_slave_2_r_bits_user(1'b0), // TODO check this
12321207

12331208
.io_slave_3_aw_ready(fsimtop_s_3_axi_awready),
12341209
.io_slave_3_aw_valid(fsimtop_s_3_axi_awvalid),
@@ -1240,23 +1215,18 @@ wire fsimtop_s_3_axi_rready;
12401215
.io_slave_3_aw_bits_cache(fsimtop_s_3_axi_awcache), // not available on DDR IF
12411216
.io_slave_3_aw_bits_prot(fsimtop_s_3_axi_awprot), // not available on DDR IF
12421217
.io_slave_3_aw_bits_qos(fsimtop_s_3_axi_awqos), // not available on DDR IF
1243-
.io_slave_3_aw_bits_region(fsimtop_s_3_axi_awregion), // not available on DDR IF
12441218
.io_slave_3_aw_bits_id(fsimtop_s_3_axi_awid),
1245-
.io_slave_3_aw_bits_user(), // not available on DDR IF
12461219

12471220
.io_slave_3_w_ready(fsimtop_s_3_axi_wready),
12481221
.io_slave_3_w_valid(fsimtop_s_3_axi_wvalid),
12491222
.io_slave_3_w_bits_data(fsimtop_s_3_axi_wdata),
12501223
.io_slave_3_w_bits_last(fsimtop_s_3_axi_wlast),
1251-
.io_slave_3_w_bits_id(),
12521224
.io_slave_3_w_bits_strb(fsimtop_s_3_axi_wstrb),
1253-
.io_slave_3_w_bits_user(), // not available on DDR IF
12541225

12551226
.io_slave_3_b_ready(fsimtop_s_3_axi_bready),
12561227
.io_slave_3_b_valid(fsimtop_s_3_axi_bvalid),
12571228
.io_slave_3_b_bits_resp(fsimtop_s_3_axi_bresp),
12581229
.io_slave_3_b_bits_id(fsimtop_s_3_axi_bid),
1259-
.io_slave_3_b_bits_user(1'b0), // TODO check this
12601230

12611231
.io_slave_3_ar_ready(fsimtop_s_3_axi_arready),
12621232
.io_slave_3_ar_valid(fsimtop_s_3_axi_arvalid),
@@ -1268,18 +1238,14 @@ wire fsimtop_s_3_axi_rready;
12681238
.io_slave_3_ar_bits_cache(fsimtop_s_3_axi_arcache), // not available on DDR IF
12691239
.io_slave_3_ar_bits_prot(fsimtop_s_3_axi_arprot), // not available on DDR IF
12701240
.io_slave_3_ar_bits_qos(fsimtop_s_3_axi_arqos), // not available on DDR IF
1271-
.io_slave_3_ar_bits_region(fsimtop_s_3_axi_arregion), // not available on DDR IF
12721241
.io_slave_3_ar_bits_id(fsimtop_s_3_axi_arid), // not available on DDR IF
1273-
.io_slave_3_ar_bits_user(), // not available on DDR IF
12741242

12751243
.io_slave_3_r_ready(fsimtop_s_3_axi_rready),
12761244
.io_slave_3_r_valid(fsimtop_s_3_axi_rvalid),
12771245
.io_slave_3_r_bits_resp(fsimtop_s_3_axi_rresp),
12781246
.io_slave_3_r_bits_data(fsimtop_s_3_axi_rdata),
12791247
.io_slave_3_r_bits_last(fsimtop_s_3_axi_rlast),
1280-
.io_slave_3_r_bits_id(fsimtop_s_3_axi_rid),
1281-
.io_slave_3_r_bits_user(1'b0) // TODO check this
1282-
1248+
.io_slave_3_r_bits_id(fsimtop_s_3_axi_rid)
12831249
);
12841250

12851251
// assign cl_sh_ddr_awsize = 3'b110;

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