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jerryz123jerryz123
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Add strategy to remove -retime flag from Vivado
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7 files changed

+64
-6
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7 files changed

+64
-6
lines changed

‎hdk/cl/developer_designs/cl_firesim/build/scripts/synth_cl_firesim.tcl

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@@ -117,7 +117,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
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update_compile_order -fileset sources_1
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puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
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eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive -retiming]
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eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
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set failval [catch {exec grep "FAIL" failfast.csv}]
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if { $failval==0 } {

‎hdk/common/shell_v04261818/build/scripts/strategy_BASIC.tcl

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@@ -16,7 +16,7 @@
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source $HDK_SHELL_DIR/build/scripts/params.tcl
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source $HDK_SHELL_DIR/build/scripts/uram_options.tcl
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set synth_options "-keep_equivalent_registers $synth_uram_option"
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set synth_options "-keep_equivalent_registers $synth_uram_option -retiming"
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set synth_directive "default"
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#Set psip to 1 to enable Physical Synthesis in Placer

‎hdk/common/shell_v04261818/build/scripts/strategy_CONGESTION.tcl

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@@ -16,7 +16,7 @@
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source $HDK_SHELL_DIR/build/scripts/params.tcl
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source $HDK_SHELL_DIR/build/scripts/uram_options.tcl
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set synth_options "-no_lc -shreg_min_size 10 -control_set_opt_threshold 16 $synth_uram_option"
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set synth_options "-no_lc -shreg_min_size 10 -control_set_opt_threshold 16 $synth_uram_option -retiming"
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set synth_directive "AlternateRoutability"
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#Set psip to 1 to enable Physical Synthesis in Placer

‎hdk/common/shell_v04261818/build/scripts/strategy_DEFAULT.tcl

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@@ -16,7 +16,7 @@
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source $HDK_SHELL_DIR/build/scripts/params.tcl
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source $HDK_SHELL_DIR/build/scripts/uram_options.tcl
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set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option"
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set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option -retiming"
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set synth_directive "default"
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#Set psip to 1 to enable Physical Synthesis in Placer

‎hdk/common/shell_v04261818/build/scripts/strategy_EXPLORE.tcl

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@@ -16,7 +16,7 @@
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source $HDK_SHELL_DIR/build/scripts/params.tcl
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source $HDK_SHELL_DIR/build/scripts/uram_options.tcl
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set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option"
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set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option -retiming"
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set synth_directive "default"
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#Set psip to 1 to enable Physical Synthesis in Placer

‎hdk/common/shell_v04261818/build/scripts/strategy_NORETIMING.tcl

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@@ -0,0 +1,58 @@
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# Amazon FPGA Hardware Development Kit
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#
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# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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#
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# Licensed under the Amazon Software License (the "License"). You may not use
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# this file except in compliance with the License. A copy of the License is
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# located at
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#
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# http://aws.amazon.com/asl/
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#
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# or in the "license" file accompanying this file. This file is distributed on
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# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
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# implied. See the License for the specific language governing permissions and
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# limitations under the License.
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source $HDK_SHELL_DIR/build/scripts/params.tcl
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source $HDK_SHELL_DIR/build/scripts/uram_options.tcl
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set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option"
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set synth_directive "default"
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#Set psip to 1 to enable Physical Synthesis in Placer
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set psip 0
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set link 1
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set opt 1
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set opt_options ""
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set opt_directive "Explore"
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set opt_preHookTcl "$HDK_SHELL_DIR/build/scripts/check_uram.tcl"
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set opt_postHookTcl "$HDK_SHELL_DIR/build/scripts/apply_debug_constraints.tcl"
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set place 1
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set place_options ""
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set place_directive "ExtraNetDelay_high"
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set place_preHookTcl ""
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set place_postHookTcl ""
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set phys_opt 1
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set phys_options ""
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set phys_directive ""
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set phys_directive "AggressiveExplore"
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set phys_preHookTcl ""
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set phys_postHookTcl ""
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set route 1
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set route_options "-tns_cleanup"
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set route_directive "Explore"
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set route_preHookTcl ""
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set route_postHookTcl ""
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set route_phys_opt 1
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set post_phys_options ""
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set post_phys_directive "AggressiveExplore"
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set post_phys_preHookTcl ""
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set post_phys_postHookTcl ""
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‎hdk/common/shell_v04261818/build/scripts/strategy_TIMING.tcl

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@@ -16,7 +16,7 @@
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source $HDK_SHELL_DIR/build/scripts/params.tcl
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source $HDK_SHELL_DIR/build/scripts/uram_options.tcl
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set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option"
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set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option -retiming"
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set synth_directive "default"
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#Set psip to 1 to enable Physical Synthesis in Placer

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