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hdk/cl/developer_designs/cl_firesim/build/scripts
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lines changed Original file line number Diff line number Diff line change @@ -311,18 +311,12 @@ if {$implement} {
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# #############################
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# CL Post-Route Optimization
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# #############################
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- set SLACK [get_property SLACK [get_timing_paths]]
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+ set SLACK [get_property -min SLACK [get_timing_paths -delay_type min_max ]]
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# Post-route phys_opt will not be run if slack is positive or greater than -200ps.
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if {$route_phys_opt && $SLACK > -0.400 && $SLACK < 0} {
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puts " \n AWS FPGA: ([ clock format [clock seconds] -format %T]) - Running post-route optimization" ;
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impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl
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}
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- # Check if slack has improved after physopt.
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- set SLACK [get_property SLACK [get_timing_paths]]
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- if {$SLACK < 0} {
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- puts " \n FATAL: Design did not meet timing requirements. Terminating." ;
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- exit 3
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- }
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# #############################
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# Final Implmentation Steps
@@ -347,6 +341,13 @@ if {$implement} {
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# Generate debug probes file
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write_debug_probes -force -no_partial_ltxfile -file $CL_DIR /build/checkpoints/${timestamp} .debug_probes.ltx
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+ # Before proceeding, coarsely check if we meet timing otherwise exit
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+ set SLACK [get_property -min SLACK [get_timing_paths -delay_type min_max]]
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+ if {$SLACK < 0} {
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+ puts " \n FATAL: Design did not meet timing requirements. Terminating." ;
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+ exit 3
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+ }
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+
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close_project
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}
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