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davidbiancolindavidbiancolin
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Merge pull request #25 from firesim/dev
FireSim 1.10.0 Release (Dev -> Master PR)
2 parents e408dc3 + e292b3d commit 65deb47

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8 files changed

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-57
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8 files changed

+40
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‎hdk/cl/developer_designs/cl_firesim/design/cl_firesim.sv

Lines changed: 1 addition & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1089,23 +1089,18 @@ wire fsimtop_s_3_axi_rready;
10891089
.io_slave_0_aw_bits_cache(fsimtop_s_0_axi_awcache), // not available on DDR IF
10901090
.io_slave_0_aw_bits_prot(fsimtop_s_0_axi_awprot), // not available on DDR IF
10911091
.io_slave_0_aw_bits_qos(fsimtop_s_0_axi_awqos), // not available on DDR IF
1092-
.io_slave_0_aw_bits_region(fsimtop_s_0_axi_awregion), // not available on DDR IF
10931092
.io_slave_0_aw_bits_id(fsimtop_s_0_axi_awid),
1094-
.io_slave_0_aw_bits_user(), // not available on DDR IF
10951093

10961094
.io_slave_0_w_ready(fsimtop_s_0_axi_wready),
10971095
.io_slave_0_w_valid(fsimtop_s_0_axi_wvalid),
10981096
.io_slave_0_w_bits_data(fsimtop_s_0_axi_wdata),
10991097
.io_slave_0_w_bits_last(fsimtop_s_0_axi_wlast),
1100-
.io_slave_0_w_bits_id(),
11011098
.io_slave_0_w_bits_strb(fsimtop_s_0_axi_wstrb),
1102-
.io_slave_0_w_bits_user(), // not available on DDR IF
11031099

11041100
.io_slave_0_b_ready(fsimtop_s_0_axi_bready),
11051101
.io_slave_0_b_valid(fsimtop_s_0_axi_bvalid),
11061102
.io_slave_0_b_bits_resp(fsimtop_s_0_axi_bresp),
11071103
.io_slave_0_b_bits_id(fsimtop_s_0_axi_bid),
1108-
.io_slave_0_b_bits_user(1'b0), // TODO check this
11091104

11101105
.io_slave_0_ar_ready(fsimtop_s_0_axi_arready),
11111106
.io_slave_0_ar_valid(fsimtop_s_0_axi_arvalid),
@@ -1117,17 +1112,14 @@ wire fsimtop_s_3_axi_rready;
11171112
.io_slave_0_ar_bits_cache(fsimtop_s_0_axi_arcache), // not available on DDR IF
11181113
.io_slave_0_ar_bits_prot(fsimtop_s_0_axi_arprot), // not available on DDR IF
11191114
.io_slave_0_ar_bits_qos(fsimtop_s_0_axi_arqos), // not available on DDR IF
1120-
.io_slave_0_ar_bits_region(fsimtop_s_0_axi_arregion), // not available on DDR IF
11211115
.io_slave_0_ar_bits_id(fsimtop_s_0_axi_arid), // not available on DDR IF
1122-
.io_slave_0_ar_bits_user(), // not available on DDR IF
11231116

11241117
.io_slave_0_r_ready(fsimtop_s_0_axi_rready),
11251118
.io_slave_0_r_valid(fsimtop_s_0_axi_rvalid),
11261119
.io_slave_0_r_bits_resp(fsimtop_s_0_axi_rresp),
11271120
.io_slave_0_r_bits_data(fsimtop_s_0_axi_rdata),
11281121
.io_slave_0_r_bits_last(fsimtop_s_0_axi_rlast),
11291122
.io_slave_0_r_bits_id(fsimtop_s_0_axi_rid),
1130-
.io_slave_0_r_bits_user(1'b0), // TODO check this
11311123

11321124
.io_slave_1_aw_ready(fsimtop_s_1_axi_awready),
11331125
.io_slave_1_aw_valid(fsimtop_s_1_axi_awvalid),
@@ -1139,23 +1131,18 @@ wire fsimtop_s_3_axi_rready;
11391131
.io_slave_1_aw_bits_cache(fsimtop_s_1_axi_awcache), // not available on DDR IF
11401132
.io_slave_1_aw_bits_prot(fsimtop_s_1_axi_awprot), // not available on DDR IF
11411133
.io_slave_1_aw_bits_qos(fsimtop_s_1_axi_awqos), // not available on DDR IF
1142-
.io_slave_1_aw_bits_region(fsimtop_s_1_axi_awregion), // not available on DDR IF
11431134
.io_slave_1_aw_bits_id(fsimtop_s_1_axi_awid),
1144-
.io_slave_1_aw_bits_user(), // not available on DDR IF
11451135

11461136
.io_slave_1_w_ready(fsimtop_s_1_axi_wready),
11471137
.io_slave_1_w_valid(fsimtop_s_1_axi_wvalid),
11481138
.io_slave_1_w_bits_data(fsimtop_s_1_axi_wdata),
11491139
.io_slave_1_w_bits_last(fsimtop_s_1_axi_wlast),
1150-
.io_slave_1_w_bits_id(),
11511140
.io_slave_1_w_bits_strb(fsimtop_s_1_axi_wstrb),
1152-
.io_slave_1_w_bits_user(), // not available on DDR IF
11531141

11541142
.io_slave_1_b_ready(fsimtop_s_1_axi_bready),
11551143
.io_slave_1_b_valid(fsimtop_s_1_axi_bvalid),
11561144
.io_slave_1_b_bits_resp(fsimtop_s_1_axi_bresp),
11571145
.io_slave_1_b_bits_id(fsimtop_s_1_axi_bid),
1158-
.io_slave_1_b_bits_user(1'b0), // TODO check this
11591146

11601147
.io_slave_1_ar_ready(fsimtop_s_1_axi_arready),
11611148
.io_slave_1_ar_valid(fsimtop_s_1_axi_arvalid),
@@ -1167,18 +1154,14 @@ wire fsimtop_s_3_axi_rready;
11671154
.io_slave_1_ar_bits_cache(fsimtop_s_1_axi_arcache), // not available on DDR IF
11681155
.io_slave_1_ar_bits_prot(fsimtop_s_1_axi_arprot), // not available on DDR IF
11691156
.io_slave_1_ar_bits_qos(fsimtop_s_1_axi_arqos), // not available on DDR IF
1170-
.io_slave_1_ar_bits_region(fsimtop_s_1_axi_arregion), // not available on DDR IF
11711157
.io_slave_1_ar_bits_id(fsimtop_s_1_axi_arid), // not available on DDR IF
1172-
.io_slave_1_ar_bits_user(), // not available on DDR IF
11731158

11741159
.io_slave_1_r_ready(fsimtop_s_1_axi_rready),
11751160
.io_slave_1_r_valid(fsimtop_s_1_axi_rvalid),
11761161
.io_slave_1_r_bits_resp(fsimtop_s_1_axi_rresp),
11771162
.io_slave_1_r_bits_data(fsimtop_s_1_axi_rdata),
11781163
.io_slave_1_r_bits_last(fsimtop_s_1_axi_rlast),
11791164
.io_slave_1_r_bits_id(fsimtop_s_1_axi_rid),
1180-
.io_slave_1_r_bits_user(1'b0), // TODO check this
1181-
11821165

11831166
.io_slave_2_aw_ready(fsimtop_s_2_axi_awready),
11841167
.io_slave_2_aw_valid(fsimtop_s_2_axi_awvalid),
@@ -1190,23 +1173,18 @@ wire fsimtop_s_3_axi_rready;
11901173
.io_slave_2_aw_bits_cache(fsimtop_s_2_axi_awcache), // not available on DDR IF
11911174
.io_slave_2_aw_bits_prot(fsimtop_s_2_axi_awprot), // not available on DDR IF
11921175
.io_slave_2_aw_bits_qos(fsimtop_s_2_axi_awqos), // not available on DDR IF
1193-
.io_slave_2_aw_bits_region(fsimtop_s_2_axi_awregion), // not available on DDR IF
11941176
.io_slave_2_aw_bits_id(fsimtop_s_2_axi_awid),
1195-
.io_slave_2_aw_bits_user(), // not available on DDR IF
11961177

11971178
.io_slave_2_w_ready(fsimtop_s_2_axi_wready),
11981179
.io_slave_2_w_valid(fsimtop_s_2_axi_wvalid),
11991180
.io_slave_2_w_bits_data(fsimtop_s_2_axi_wdata),
12001181
.io_slave_2_w_bits_last(fsimtop_s_2_axi_wlast),
1201-
.io_slave_2_w_bits_id(),
12021182
.io_slave_2_w_bits_strb(fsimtop_s_2_axi_wstrb),
1203-
.io_slave_2_w_bits_user(), // not available on DDR IF
12041183

12051184
.io_slave_2_b_ready(fsimtop_s_2_axi_bready),
12061185
.io_slave_2_b_valid(fsimtop_s_2_axi_bvalid),
12071186
.io_slave_2_b_bits_resp(fsimtop_s_2_axi_bresp),
12081187
.io_slave_2_b_bits_id(fsimtop_s_2_axi_bid),
1209-
.io_slave_2_b_bits_user(1'b0), // TODO check this
12101188

12111189
.io_slave_2_ar_ready(fsimtop_s_2_axi_arready),
12121190
.io_slave_2_ar_valid(fsimtop_s_2_axi_arvalid),
@@ -1218,17 +1196,14 @@ wire fsimtop_s_3_axi_rready;
12181196
.io_slave_2_ar_bits_cache(fsimtop_s_2_axi_arcache), // not available on DDR IF
12191197
.io_slave_2_ar_bits_prot(fsimtop_s_2_axi_arprot), // not available on DDR IF
12201198
.io_slave_2_ar_bits_qos(fsimtop_s_2_axi_arqos), // not available on DDR IF
1221-
.io_slave_2_ar_bits_region(fsimtop_s_2_axi_arregion), // not available on DDR IF
12221199
.io_slave_2_ar_bits_id(fsimtop_s_2_axi_arid), // not available on DDR IF
1223-
.io_slave_2_ar_bits_user(), // not available on DDR IF
12241200

12251201
.io_slave_2_r_ready(fsimtop_s_2_axi_rready),
12261202
.io_slave_2_r_valid(fsimtop_s_2_axi_rvalid),
12271203
.io_slave_2_r_bits_resp(fsimtop_s_2_axi_rresp),
12281204
.io_slave_2_r_bits_data(fsimtop_s_2_axi_rdata),
12291205
.io_slave_2_r_bits_last(fsimtop_s_2_axi_rlast),
12301206
.io_slave_2_r_bits_id(fsimtop_s_2_axi_rid),
1231-
.io_slave_2_r_bits_user(1'b0), // TODO check this
12321207

12331208
.io_slave_3_aw_ready(fsimtop_s_3_axi_awready),
12341209
.io_slave_3_aw_valid(fsimtop_s_3_axi_awvalid),
@@ -1240,23 +1215,18 @@ wire fsimtop_s_3_axi_rready;
12401215
.io_slave_3_aw_bits_cache(fsimtop_s_3_axi_awcache), // not available on DDR IF
12411216
.io_slave_3_aw_bits_prot(fsimtop_s_3_axi_awprot), // not available on DDR IF
12421217
.io_slave_3_aw_bits_qos(fsimtop_s_3_axi_awqos), // not available on DDR IF
1243-
.io_slave_3_aw_bits_region(fsimtop_s_3_axi_awregion), // not available on DDR IF
12441218
.io_slave_3_aw_bits_id(fsimtop_s_3_axi_awid),
1245-
.io_slave_3_aw_bits_user(), // not available on DDR IF
12461219

12471220
.io_slave_3_w_ready(fsimtop_s_3_axi_wready),
12481221
.io_slave_3_w_valid(fsimtop_s_3_axi_wvalid),
12491222
.io_slave_3_w_bits_data(fsimtop_s_3_axi_wdata),
12501223
.io_slave_3_w_bits_last(fsimtop_s_3_axi_wlast),
1251-
.io_slave_3_w_bits_id(),
12521224
.io_slave_3_w_bits_strb(fsimtop_s_3_axi_wstrb),
1253-
.io_slave_3_w_bits_user(), // not available on DDR IF
12541225

12551226
.io_slave_3_b_ready(fsimtop_s_3_axi_bready),
12561227
.io_slave_3_b_valid(fsimtop_s_3_axi_bvalid),
12571228
.io_slave_3_b_bits_resp(fsimtop_s_3_axi_bresp),
12581229
.io_slave_3_b_bits_id(fsimtop_s_3_axi_bid),
1259-
.io_slave_3_b_bits_user(1'b0), // TODO check this
12601230

12611231
.io_slave_3_ar_ready(fsimtop_s_3_axi_arready),
12621232
.io_slave_3_ar_valid(fsimtop_s_3_axi_arvalid),
@@ -1268,18 +1238,14 @@ wire fsimtop_s_3_axi_rready;
12681238
.io_slave_3_ar_bits_cache(fsimtop_s_3_axi_arcache), // not available on DDR IF
12691239
.io_slave_3_ar_bits_prot(fsimtop_s_3_axi_arprot), // not available on DDR IF
12701240
.io_slave_3_ar_bits_qos(fsimtop_s_3_axi_arqos), // not available on DDR IF
1271-
.io_slave_3_ar_bits_region(fsimtop_s_3_axi_arregion), // not available on DDR IF
12721241
.io_slave_3_ar_bits_id(fsimtop_s_3_axi_arid), // not available on DDR IF
1273-
.io_slave_3_ar_bits_user(), // not available on DDR IF
12741242

12751243
.io_slave_3_r_ready(fsimtop_s_3_axi_rready),
12761244
.io_slave_3_r_valid(fsimtop_s_3_axi_rvalid),
12771245
.io_slave_3_r_bits_resp(fsimtop_s_3_axi_rresp),
12781246
.io_slave_3_r_bits_data(fsimtop_s_3_axi_rdata),
12791247
.io_slave_3_r_bits_last(fsimtop_s_3_axi_rlast),
1280-
.io_slave_3_r_bits_id(fsimtop_s_3_axi_rid),
1281-
.io_slave_3_r_bits_user(1'b0) // TODO check this
1282-
1248+
.io_slave_3_r_bits_id(fsimtop_s_3_axi_rid)
12831249
);
12841250

12851251
// assign cl_sh_ddr_awsize = 3'b110;

‎hdk/cl/developer_designs/cl_firesim/software/runtime/common_dma.c

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -163,22 +163,23 @@ int fpga_driver_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffe
163163
return rc;
164164
}
165165

166-
void fpga_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address) {
167-
#ifdef SV_TEST
168-
sv_fpga_start_cl_to_buffer(slot_id, channel, buffer_size, address);
169-
#else
170-
fpga_driver_read_cl_to_buffer(slot_id, channel, fd, buffer_size, address);
171-
#endif
172-
dma_memcmp(buffer_size);
173-
}
174-
175-
void fpga_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buffer_size, size_t address){
176-
#ifdef SV_TEST
177-
sv_fpga_start_buffer_to_cl(slot_id, channel, buffer_size, write_buffer, address);
178-
#else
179-
fpga_driver_write_buffer_to_cl(slot_id, channel, fd, buffer_size, address);
180-
#endif
181-
}
166+
// Biancolin: We don't use these but their callouts to the SV task that implements them has changed.
167+
//void fpga_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address) {
168+
//#ifdef SV_TEST
169+
// sv_fpga_start_cl_to_buffer(slot_id, channel, buffer_size, address);
170+
//#else
171+
// fpga_driver_read_cl_to_buffer(slot_id, channel, fd, buffer_size, address);
172+
//#endif
173+
// dma_memcmp(buffer_size);
174+
//}
175+
//
176+
//void fpga_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buffer_size, size_t address){
177+
//#ifdef SV_TEST
178+
// sv_fpga_start_buffer_to_cl(slot_id, channel, buffer_size, write_buffer, address);
179+
//#else
180+
// fpga_driver_write_buffer_to_cl(slot_id, channel, fd, buffer_size, address);
181+
//#endif
182+
//}
182183

183184
int dma_memcmp (size_t buffer_size) {
184185
int rc = 0;

‎hdk/cl/developer_designs/cl_firesim/software/runtime/common_dma.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,10 @@ int fpga_driver_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buff
5555

5656
int fpga_driver_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
5757

58-
void fpga_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
59-
60-
void fpga_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
58+
// Biancolin: We don't use these but their callouts to the SV task that implements them has changed.
59+
//void fpga_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
60+
//
61+
//void fpga_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
6162

6263
int dma_example_hwsw_cosim(int slot_id);
6364

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/Makefile

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,11 +57,16 @@ export SH_SH_DIR = $(HDK_SHELL_DESIGN_DIR)/sh_ddr/sim
5757
SV_TEST_LIST = test_firesim
5858
C_FILES = $(C_TEST_NAME) $(C_SDK_USR_UTILS_DIR)/sh_dpi_tasks.c $(C_COMMON_DIR)/src/fpga_pci_sv.c $(C_SRC_DIR)/common_dma.c
5959

60+
ELABORATED_IP_FILES = $(CL_ROOT)/ip/clk_wiz_0_firesim/clk_wiz_0_firesim_sim_netlist.v
61+
6062
ifeq ($(XCHK), 1)
6163
all: make_sim_dir compile_chk run
6264
else
6365
all: make_sim_dir compile run
6466
endif
6567

68+
$(CL_ROOT)/ip/clk_wiz_0_firesim/clk_wiz_0_firesim_sim_netlist.v:
69+
vivado -mode tcl -source synth_firesim_clk_wiz_sim.tcl -tclargs $(CL_ROOT)
70+
6671
include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc
6772

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/Makefile.vcs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,11 +22,11 @@
2222
## 2. make all VCS=1 -> Runs the test
2323
##################################################################
2424

25-
compile: $(COMPLIB_DIR)
25+
compile: $(COMPLIB_DIR) $(ELABORATED_IP_FILES)
2626
mkdir -p $(SIM_DIR)
2727
cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup
2828
cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS +define+DMA_TEST $(DEFINES) +lint=TFIPC-L
29-
cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" "-I$(C_SRC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
29+
cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" "-I$(C_SRC_DIR)" -debug_all -M -debug_access+nomemcbk+dmptf -debug_region+cell +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
3030

3131
run:
3232

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/Makefile.vivado

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
## Makefile For Vivado compiles and simulations
1818
##################################################################
1919

20-
compile:
20+
compile: $(ELABORATED_IP_FILES)
2121
mkdir -p $(SIM_DIR)
2222
cd $(SIM_DIR) && xsc $(C_FILES) --additional_option "-I$(C_SDK_USR_INC_DIR)" --additional_option "-I$(C_SDK_USR_UTILS_DIR)" --additional_option "-I$(C_COMMON_DIR)/include" --additional_option "-I$(C_COMMON_DIR)/src" --additional_option "-I$(C_INC_DIR)" --additional_option "-DVIVADO_SIM" --additional_option "-DSV_TEST" --additional_option "-DDMA_TEST"
2323
cd $(SIM_DIR) && xvlog --sv -m64 --define DMA_TEST --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --work xil_defaultlib --relax -f $(SCRIPTS_DIR)/top.vivado.f

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/synth_firesim_clk_wiz_sim.tcl

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
set CL_DIR [lindex $argv 0]
2+
create_project -in_memory -part xcvu9p-flgb2104-2-i -force
3+
source $CL_DIR/design/cl_firesim_generated_env.tcl
4+
source $CL_DIR/build/scripts/synth_firesim_clk_wiz.tcl
5+
exit

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vcs.f

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
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-y ${CL_ROOT}/../common/design
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-y ${CL_ROOT}/design
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-y ${CL_ROOT}/design/ila_files
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-y ${CL_ROOT}/verif/sv
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-y ${SH_LIB_DIR}
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-y ${SH_INF_DIR}
@@ -37,6 +38,7 @@
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+incdir+${CL_ROOT}/../common/design
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+incdir+${CL_ROOT}/design
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+incdir+${CL_ROOT}/design/ila_files
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+incdir+${CL_ROOT}/verif/sv
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+incdir+${SH_LIB_DIR}
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+incdir+${SH_INF_DIR}
@@ -76,6 +78,9 @@
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${CL_ROOT}/ip/axi_dwidth_converter_0/sim/axi_dwidth_converter_0.v
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${CL_ROOT}/ip/axi_dwidth_converter_0/hdl/axi_dwidth_converter_v2_1_vl_rfs.v
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${CL_ROOT}/ip/axi_dwidth_converter_0/hdl/axi_register_slice_v2_1_vl_rfs.v
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${CL_ROOT}/design/ila_files/firesim_ila_insert_inst.v
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${CL_ROOT}/design/ila_files/firesim_ila_insert_ports.v
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${CL_ROOT}/design/ila_files/firesim_ila_insert_wires.v
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${CL_ROOT}/design/cl_firesim_generated.sv
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${CL_ROOT}/design/cl_firesim_generated_defines.vh
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${CL_ROOT}/design/cl_firesim.sv

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