Skip to content

ffq513/UART_VLC_Transmission

BranchesTags
 
 

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

6 Commits
.qsys_edit
.qsys_edit
 
 
db
db
 
 
greybox_tmp
greybox_tmp
 
 
incremental_db
incremental_db
 
 
manual_rst
manual_rst
 
 
output_files
output_files
 
 
reed_solomon-library
reed_solomon-library
 
 
simulation/modelsim
simulation/modelsim
 
 
src
src
 
 
syn_threshold
syn_threshold
 
 
wait_time_threshold
wait_time_threshold
 
 
README.md
README.md
 
 
RS_DE_LANE_QUATUS.html
RS_DE_LANE_QUATUS.html
 
 
RS_DE_LANE_QUATUS.qip
RS_DE_LANE_QUATUS.qip
 
 
RS_DE_LANE_QUATUS.v
RS_DE_LANE_QUATUS.v
 
 
RS_DE_LANE_QUATUS.vo
RS_DE_LANE_QUATUS.vo
 
 
RS_DE_LANE_QUATUS_bb.v
RS_DE_LANE_QUATUS_bb.v
 
 
RS_DE_LANE_QUATUS_block_period_stim.txt
RS_DE_LANE_QUATUS_block_period_stim.txt
 
 
RS_DE_LANE_QUATUS_encoded_data.txt
RS_DE_LANE_QUATUS_encoded_data.txt
 
 
RS_DE_LANE_QUATUS_inv_8_285.hex
RS_DE_LANE_QUATUS_inv_8_285.hex
 
 
RS_DE_LANE_QUATUS_nativelink.tcl
RS_DE_LANE_QUATUS_nativelink.tcl
 
 
RS_DE_LANE_QUATUS_syn.v
RS_DE_LANE_QUATUS_syn.v
 
 
RS_DE_LANE_QUATUS_testbench.v
RS_DE_LANE_QUATUS_testbench.v
 
 
RS_DE_LANE_QUATUS_vsim_script.tcl
RS_DE_LANE_QUATUS_vsim_script.tcl
 
 
RS_ENC_LANE_QUATUS.html
RS_ENC_LANE_QUATUS.html
 
 
RS_ENC_LANE_QUATUS.qip
RS_ENC_LANE_QUATUS.qip
 
 
RS_ENC_LANE_QUATUS.v
RS_ENC_LANE_QUATUS.v
 
 
RS_ENC_LANE_QUATUS.vo
RS_ENC_LANE_QUATUS.vo
 
 
RS_ENC_LANE_QUATUS_bb.v
RS_ENC_LANE_QUATUS_bb.v
 
 
RS_ENC_LANE_QUATUS_block_period_stim.txt
RS_ENC_LANE_QUATUS_block_period_stim.txt
 
 
RS_ENC_LANE_QUATUS_encoded_data.txt
RS_ENC_LANE_QUATUS_encoded_data.txt
 
 
RS_ENC_LANE_QUATUS_nativelink.tcl
RS_ENC_LANE_QUATUS_nativelink.tcl
 
 
RS_ENC_LANE_QUATUS_syn.v
RS_ENC_LANE_QUATUS_syn.v
 
 
RS_ENC_LANE_QUATUS_testbench.v
RS_ENC_LANE_QUATUS_testbench.v
 
 
RS_ENC_LANE_QUATUS_vsim_script.tcl
RS_ENC_LANE_QUATUS_vsim_script.tcl
 
 
clk_gen.ppf
clk_gen.ppf
 
 
clk_gen.qip
clk_gen.qip
 
 
clk_gen.v
clk_gen.v
 
 
clk_gen_1.ppf
clk_gen_1.ppf
 
 
clk_gen_1.qip
clk_gen_1.qip
 
 
clk_gen_1.v
clk_gen_1.v
 
 
clk_gen_1_bb.v
clk_gen_1_bb.v
 
 
clk_gen_bb.v
clk_gen_bb.v
 
 
desyn.stp
desyn.stp
 
 
desyn2.stp
desyn2.stp
 
 
fifo_2_pcs_tx_interface.stp
fifo_2_pcs_tx_interface.stp
 
 
fifo_rx.qip
fifo_rx.qip
 
 
fifo_rx.v
fifo_rx.v
 
 
fifo_rx_bb.v
fifo_rx_bb.v
 
 
fifo_tx.qip
fifo_tx.qip
 
 
fifo_tx.v
fifo_tx.v
 
 
fifo_tx_2_pcs.stp
fifo_tx_2_pcs.stp
 
 
fifo_tx_bb.v
fifo_tx_bb.v
 
 
fifo_tx_input.stp
fifo_tx_input.stp
 
 
fsmc_tx.stp
fsmc_tx.stp
 
 
m_r_clk_gen.ppf
m_r_clk_gen.ppf
 
 
m_r_clk_gen.qip
m_r_clk_gen.qip
 
 
m_r_clk_gen.v
m_r_clk_gen.v
 
 
m_r_clk_gen_bb.v
m_r_clk_gen_bb.v
 
 
manual_rst.qsys
manual_rst.qsys
 
 
manual_rst.sopcinfo
manual_rst.sopcinfo
 
 
my_ps.sopcinfo
my_ps.sopcinfo
 
 
nios2_SG_DMA_test.ipregen.rpt
nios2_SG_DMA_test.ipregen.rpt
 
 
nios2_SG_DMA_test.qpf
nios2_SG_DMA_test.qpf
 
 
nios2_SG_DMA_test.qsf
nios2_SG_DMA_test.qsf
 
 
nios2_SG_DMA_test.qws
nios2_SG_DMA_test.qws
 
 
nios2_SG_DMA_test_nativelink_simulation.rpt
nios2_SG_DMA_test_nativelink_simulation.rpt
 
 
rx_interface.stp
rx_interface.stp
 
 
rx_rs.stp
rx_rs.stp
 
 
rx_s.stp
rx_s.stp
 
 
syn_threshold.qsys
syn_threshold.qsys
 
 
syn_threshold.sopcinfo
syn_threshold.sopcinfo
 
 
tx.stp
tx.stp
 
 
tx_rs.stp
tx_rs.stp
 
 
vlc_fsmc_2system_0816.rbf
vlc_fsmc_2system_0816.rbf
 
 
wait_time_threshold.qsys
wait_time_threshold.qsys
 
 
wait_time_threshold.sopcinfo
wait_time_threshold.sopcinfo
 
 

Repository files navigation

UART_VLC_Transmission

UART (9600/115200) to VLC (RS code/Manchester code/8x Sampling Syncronization) Quatus 18.0 project problem: RS decoder do not support full-rate (check length is too long)

About

UART (9600/115200) to VLC (RS code/Manchester code/8x Sampling Syncronization)

Resources

Readme
Activity

Stars

0 stars

Watchers

0 watching

Forks

0 forks
Report repository

Releases

No releases published

Packages

No packages published

Languages

  • Verilog 49.6%
  • VHDL 39.2%
  • HTML 4.6%
  • Rocq Prover 3.4%
  • SystemVerilog 3.0%
  • Tcl 0.2%