S32 Processor

The S32 (Simple 32-bit) processor is a RISC processor with a 32-bit architecture, designed for educational purposes. It features a clean, orthogonal instruction set with a focus on simplicity and ease of understanding.

Table of Contents

• Directory Structure
• Building
• Running Tests
• Running the Emulator
• Running the Assembler
• Documentation
• RTL Implementation
• Comparison to Other Architectures
• Contributing
• License

Directory Structure

• src/: Source code for the emulator, assembler, and test framework
  • src/emulator/: Source code for the S32 emulator
  • src/s32tool/: Source code for the S32 assembler
  • src/testutil/: Legacy test utilities
  • src/s32test/: New comprehensive test framework
• include/: Header files
• docs/: Documentation
  • docs/assembly/: S32 assembly language documentation
  • docs/assembly/instructions/: Instruction reference
  • docs/assembly/basics/: Language basics
  • docs/assembly/examples/: Example programs with annotations
• examples/: Example S32 assembly programs
• build/: Build directory for binaries and test reports
• scripts/: Utility scripts
• RTL/: Register Transfer Level implementation (Verilog)

Building

To build the entire project:

make

This will build the emulator (s32emu), the assembler (s32tool), and the test framework.

Running Tests

The project includes a comprehensive testing framework called s32test. To run all tests:

make test

You can also run specific test categories:

# Test the emulator
make test-emulator

# Test the assembler
make test-assembler

# Test RTL implementation
make test-rtl

# Run tests for specific instruction types
make test-arithmetic
make test-logic
make test-memory
make test-control
make test-system

Test results are saved to the build/tests/ directory.

Legacy Tests

The project maintains an older testing framework for backward compatibility:

# Run the legacy test suite (full version)
make legacy-test

# Run the fixed version of the legacy test suite (more stable)
make legacy-test-fixed

Running the Emulator

To run the S32 emulator with an assembly file:

./s32emu examples/fibonacci.s32

The emulator supports these command-line options:

• -d: Debug mode, shows instruction-by-instruction execution
• -v: Verbose mode, provides more detailed output
• -h: Shows help message

Running the Assembler

To assemble an S32 source file:

./s32tool examples/fibonacci.s32

This creates an assembled file with the same name but with the extension .s32m (e.g., fibonacci.s32m).

Documentation

For more information about the S32 architecture, instruction set, and assembly language, see:

• Assembly Language Reference: docs/assembly/
• Instruction Set: docs/assembly/instructions/
• Programming Guide: docs/assembly/basics/
• Example Programs: docs/assembly/examples/

RTL Implementation

The RTL/ directory contains a Verilog implementation of the S32 processor that can be synthesized to FPGA or ASIC targets, such as SkyWater’s 130nm process for educational prototyping.

Comparison to Other Architectures

The S32 processor is designed for simplicity and education, but how does it stack up against other open-source 32-bit RISC architectures? The table below compares S32 to similar projects, focusing on instruction count, design goals, and suitability for ASIC implementation (e.g., 130nm).

Architecture	Instruction Count	Design Focus	Est. Gate Count (130nm)	ASIC Suitability (130nm)
S32	37	Educational, simplicity	~5k–15k	High (lean, Open MPW-ready)
RISC-V RV32I	38	Educational, extensible	~10k–15k	High (proven on Open MPW)
OpenRISC OR1200	~48	Embedded systems, OS support	~20k–30k	Moderate (larger footprint)
Ibex (RV32IMC)	~47	Embedded, code density	~10k–15k	High (taped out on 130nm)
Tiny Tapeout CPU	~20–40	Minimalist, hobbyist	~5k–10k	High (optimized for Open MPW)

• Notes:
  • S32: Compact instruction set covers core operations (ALU, memory, stack), ideal for teaching and small ASICs.
  • RISC-V RV32I: Slightly broader ISA, widely taught, with robust tools. Similar gate count to S32.
  • OpenRISC OR1200: More complex, suited for OS ports, but larger size may challenge 130nm MPW limits.
  • Ibex: Adds multiply and compressed instructions, great for embedded, matches S32’s ASIC ease.
  • Tiny Tapeout CPU: Varies widely; some are simpler than S32, optimized for tiny 130nm dies.
• Sources: RISC-V (riscv.org), OpenRISC (opencores.org), Ibex (github.com/lowRISC/ibex), Tiny Tapeout (tinytapeout.com).

Contributing

Contributions are welcome! Please submit a Pull Request or join the discussion on our community forum (replace with your repo’s Discussions link). We’re especially interested in feedback for ASIC tape-outs, such as Open MPW’s 130nm shuttle.

License

This project is distributed under the MIT License.