v4.5.0

• plugins
  • simulation
    • added simulation engine property timeout_after_sec
    • fixed load simulation input data from previous simulation in setup wizard
    • changed selection behavior in load simulation results allowing a range selection with single click
    • fixed bug in load simulation data for selected nets in graph view
    • fixed bug in external tool (saleae) to export waveform data resulting from simulation
    • changed waveform event handling so that duplicate events get blocked
    • changed waveform group value evaluation policy, first = MSB ... last = LSB
  • extended the module_identification plugin
    • added the type addition_offset that can detect an addition of inputs with an added constant offset
    • added the type constant_multiplication_offset that can detect constant multiplication with an added constant offset
    • added a more human readable description of identified functionaliyt to the data container of created modules
    • fixed segfault that occurs when the plugin tries to construct an operand with size 1
  • extended the resynthesis plugin
    • added an additional search step for a required yosys binary, that also searches locations in the PATH environment variable of the user
  • updated gate_libraries plugin
    • updated the hgl format version for the provided .hgl libraries and added the ordered attribute to all pin groups, which defaults to false
  • added scrollbar in logic evaluator plugin
  • added dataflow::Result::create_modules function that takes nothing but group IDs for easier module creation
  • added feature to import precompiled binary plugins in GUI plugin manager
  • added switch to GUI plugin manager to activate/deactivate menu contribution for plugin
• build process
  • fixed make install by updating RPATH on installation
  • fixed required minimum cmake version, demanding at least version 3.5
  • added build support for RedHat Enterprise Linux
  • fixed netlist_preprocessing build dependencies
• pin groups
  • added getter for lowest and highest index of pin group
  • added column for pin index in GUI module pin tree
  • added features to pin group context menu (change type, toggle ascending/descending)
  • fixed GUI undo function for group delete
  • changed GUI module pin tree drag'n drop behavior, allow drop pin(-group) on pin
  • changed policy when creating new pin groups, default is now descending
• gate library manager
  • added browser to list all gate types from gate library and show details for selected type
  • added wizard to create new gate types or modify existing ones
  • added wizard pages for each functional component to define gate type
  • added graphic view to preview an instance of selected or created gate type
• python
  • added python bindings gui.View for management of graph view contexts and directories
  • added a python binding that allows to create a BooleanFunction from a list of Nodes
  • added a python binding that allows simplifying a hal.BooleanFunction with simplifiaction rules for z3 expressions
  • added drag'n drop feature to drop elements from module tree in python editor thus generating code to access element
• miscellaneous
  • added user setting to suppress layout rendering upon change of module name, type, or color
  • fixed availability of "save as" so that does not required modifications to be enabaled
  • added warning message upon attempt to export project without saving recent modifications
  • added example project that comprises a AES encryption netlist with hardware trojan
  • added feature to unzip and open hal project by dropping zipped file on welcome screen
  • added get_shortest_path overload to find shortest path from gate to module successor/predecessor
  • fixed left/right arrow navigation issues when starting from selected net
  • fixed bug in node placement via GUI API
  • fixed bug in net junction routing
  • changed and unified context menus for all widgets related to netlist elements
  • added Utilities (plugin- or gate library management) and Plugins (callable actions from plugins) to main menu
  • fixed module colors not updating on creation of modules with previously used ids
  • changed the naming convention of ununsed signals in the verilog writer to include an index
  • added feature to BooleanFunctionDecorator that allows substituting of net variables to single bit extracts of pin groups
  • added shift and rotate operations to the constant propagation for simplification
  • added get_shortest_path and get_shortest_path_distance to the NetlistTraversalDecorator
  • added interactive hal screenshot to documentation wiki