HyCUBE

This work contains the RTL design for HyCUBE. Published at DAC 2017: https://www.comp.nus.edu.sg/~tulika/DAC17.pdf

Top module is chip_with_pad

spi_slave.v is downloaded from https://opencores.org/projects/spi_verilog_master_slave Memory and clock generator are proprietary IP and hence not included

Name		Name	Last commit message	Last commit date
Latest commit History 53 Commits
Tests/Pedometer_testbench_and_traces		Tests/Pedometer_testbench_and_traces
README.md		README.md
chip.sv		chip.sv
chip_with_pad.sv		chip_with_pad.sv
encoder_onehot.sv		encoder_onehot.sv
globals_network.sv		globals_network.sv
hycube.sv		hycube.sv
router.sv		router.sv
simple_alu.sv		simple_alu.sv
spi_all.sv		spi_all.sv
spi_fsm.v		spi_fsm.v
spi_slave.v		spi_slave.v
syn_fifo.v		syn_fifo.v
tile.sv		tile.sv
xbar_bypass.sv		xbar_bypass.sv

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