pre-commit: PR147599

[zyw-bot]

Link: llvm/llvm-project#147599
Requested by: @dtcxzyw

[zyw-bot]

Diff mode

runner: ariselab-64c-docker
baseline: llvm/llvm-project@7a6568d
patch: llvm/llvm-project#147599
sha256: f4ba2119ce7637272e2c73c0a103ada8d7fbc60aad7b4ef79a263edd0956f1b7
commit: d6ee61f

7 files changed, 454 insertions(+), 454 deletions(-)

Improvements:
  instcombine.NumReassoc 286963 -> 286964 +0.00%
  instcombine.NumCombined 130200109 -> 130200122 +0.00%
  instcombine.NumDeadInst 44233663 -> 44233667 +0.00%
Regressions:
  memory-builtins.ObjectVisitorLoad 2480647 -> 2480645 -0.00%

1 1 bench/darktable/optimized/RawImageDataU16.ll
29 29 bench/delta-rs/optimized/1iagj3aecrejld8d.ll
2 2 bench/openspiel/optimized/SolverIF.ll
21 21 bench/z3/optimized/sat_cut_simplifier.ll

[github-actions]

Here is a summary of the major changes in the provided LLVM IR diffs:

1. Bitwise Logic Optimization:
   In several functions (e.g., RawImageDataU16.ll, sat_cut_simplifier.ll), XOR operations were replaced with OR and AND combinations involving constants or other operands. This suggests a change in how certain bit flags or computed values are combined, possibly for correctness or optimization purposes.

2. PHI Node Source Correction:
   Multiple PHI nodes across different files (delta-rs, z3, etc.) now reference updated incoming block labels or values—such as %487 instead of %486. These likely reflect control flow graph (CFG) modifications or cleanup after earlier transformations like landing pad merging or edge splitting.

3. Switch and Branch Target Updates:
   Several switch instructions and conditional branches point to new or renamed basic blocks (e.g., %365 → %366, %390 → %391). These updates typically follow CFG restructuring or cleanup passes that renumber or merge exception handling or unwind paths.

4. Exception Handling and Landing Pad Adjustments:
   Changes in invoke/unwind destinations and landingpad use (e.g., %396 → %397, %425 → %428) indicate adjustments to exception handling paths, possibly due to landing pad merging, outlining, or cleanup during lowering or optimization.

5. Indexing and Memory Access Pattern Changes:
   Some loads and GEPs (getelementptrs) were modified, such as using %68 as an index instead of %66 in sat_cut_simplifier.ll. These suggest local register allocation changes or strength reduction optimizations altering memory access patterns.

---

High-Level Overview:
The patch primarily reflects post-optimization or codegen-level adjustments in response to control flow and exception handling changes, along with minor logic simplifications. These include CFG refinements, landing pad/exception path updates, and bitwise expression rewrites. The changes are consistent with late-stage optimizations or cleanups following earlier high-level transformations.

model: qwen-plus-latest
CompletionUsage(completion_tokens=443, prompt_tokens=9693, total_tokens=10136, completion_tokens_details=None, prompt_tokens_details=None)