A robust FIFO (First-In, First-Out) Verification Environment. It's built with SystemVerilog and leverages Object-Oriented Programming (OOP), Coverage, and Assertions to provide a comprehensive setup for verifying FIFO designs. The repository includes essential components such as assertions, FIFO and dual-port memory designs, interfaces, read and write agents, a scoreboard for data integrity, and transaction definitions.
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FIFO Verification Environment built with SystemVerilog, leveraging Object-Oriented Programming (OOP) for robust testbenches, including comprehensive Functional Coverage and SystemVerilog Assertions (SVA) for thorough design validation.
donev-stan/SystemVerilog
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FIFO Verification Environment built with SystemVerilog, leveraging Object-Oriented Programming (OOP) for robust testbenches, including comprehensive Functional Coverage and SystemVerilog Assertions (SVA) for thorough design validation.