RISC Multicycle Processor

Team Members

Tanmay Dokania
Vansh Kapoor
Navneet
Aayush Gopal

In the first phase of the task we designed the architecture of a RISC type Multi-cycle processor which is an 8-register, 16-bit computer system and is based on the Little Computer Architecture which is general enough to solve complex problems.

In its second phase we designed the architecture of a 6-stage pipelined microprocessor IITB-RISC-22(16-bit computer) that allowed predicated instruction execution and multiple load and store execution by utilizing hazard mitigation techniques like forwarding and branch prediction.

Name		Name	Last commit message	Last commit date
Latest commit History 138 Commits
QuartProj2		QuartProj2
QuartusProj		QuartusProj
RISC_pipelining_quartus		RISC_pipelining_quartus
.~lock.control.ods#		.~lock.control.ods#
.~lock.state_transition_table.xlsx#		.~lock.state_transition_table.xlsx#
Pipelined Design Document.pdf		Pipelined Design Document.pdf
QuartusProj.rar		QuartusProj.rar
README.md		README.md
RISC_pipelining_quartus.rar		RISC_pipelining_quartus.rar
alu.vhdl		alu.vhdl
control signals (1).txt		control signals (1).txt
control signals.txt		control signals.txt
control_path.vhdl		control_path.vhdl
controller.PNG		controller.PNG
create.py		create.py
data_path.vhdl		data_path.vhdl
datapath.PNG		datapath.PNG
elem.vhd		elem.vhd
left_shift.vhdl		left_shift.vhdl
lsm.vhdl		lsm.vhdl
ram_mem.vhdl		ram_mem.vhdl
registerFile.vhdl		registerFile.vhdl
riscProcessor.PNG		riscProcessor.PNG
risc_processor.vhdl		risc_processor.vhdl
state_transition.PNG		state_transition.PNG
state_transition_table.xlsx		state_transition_table.xlsx
tracefile.txt		tracefile.txt

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