Finish comments and change radix

Author: David Lavoie-Boutin

PROC/TEST2.tcl

@@ -7,43 +7,38 @@ sim:/PROCv2/id_reset\
 sim:/PROCv2/if_reset\
 sim:/PROCv2/mem_reset
 
-add wave -group "IF in buffers" sim:/PROCv2/if_pc_in_buffer\
-sim:/PROCv2/if_pc_sel_in_buffer\
-sim:/PROCv2/if_pc_enable_in_buffer
+add wave -group "IF in buffers" -radix unsigned sim:/PROCv2/if_pc_in_buffer\
+-radix binary sim:/PROCv2/if_pc_sel_in_buffer\
+-radix binary sim:/PROCv2/if_pc_enable_in_buffer
 
-add wave -group "IF out signals" sim:/PROCv2/if_pc_out\
-sim:/PROCv2/if_inst_out
+add wave -group "IF out signals" -radix unsigned sim:/PROCv2/if_pc_out\
+-radix binary sim:/PROCv2/if_inst_out
 
-add wave -group "ID in buffers" sim:/PROCv2/id_inst_in_buffer\
+add wave -group "ID in buffers" -radix binary sim:/PROCv2/id_inst_in_buffer\
 sim:/PROCv2/id_wenable_in_buffer\
-sim:/PROCv2/id_reg_add_in_buffer\
-sim:/PROCv2/id_reg_data_in_buffer\
-sim:/PROCv2/id_pc_in_buffer
+-radix unsigned sim:/PROCv2/id_reg_add_in_buffer\
+-radix binary sim:/PROCv2/id_reg_data_in_buffer\
+-radix unsigned sim:/PROCv2/id_pc_in_buffer
 
-add wave -group "ID out signals" sim:/PROCv2/id_pc_out\
+add wave -group "ID out signals" -radix unsigned sim:/PROCv2/id_pc_out\
 -radix alu sim:/PROCv2/id_alu_op_out\
-sim:/PROCv2/id_r1_out\
-sim:/PROCv2/id_r2_out\
-sim:/PROCv2/id_imm_out\
-sim:/PROCv2/id_dest_regadd_out\
-sim:/PROCv2/id_loaden_out\
+-radix decimal sim:/PROCv2/id_r1_out\
+-radix decimal sim:/PROCv2/id_r2_out\
+-radix decimal sim:/PROCv2/id_imm_out\
+-radix unsigned sim:/PROCv2/id_dest_regadd_out\
+-radix binary sim:/PROCv2/id_loaden_out\
 sim:/PROCv2/id_storeen_out\
 sim:/PROCv2/id_useimm_out\
 sim:/PROCv2/id_branch_out\
 sim:/PROCv2/id_byte_out\
 sim:/PROCv2/id_WB_enable_out
 
-add wave -group "Comaprator signals" sim:/procv2/IDstage/reg_comparator/value1\
-sim:/procv2/IDstage/reg_comparator/value2\
-sim:/procv2/IDstage/reg_comparator/ctl\
-sim:/procv2/IDstage/reg_comparator/taken
-
-add wave -group "EX in buffers" sim:/PROCv2/ex_r1_in_buffer\
-sim:/PROCv2/ex_r2_in_buffer\
-sim:/PROCv2/ex_imm_in_buffer\
-sim:/PROCv2/ex_dest_regadd_in_buffer\
-sim:/PROCv2/ex_alu_op_in_buffer\
-sim:/PROCv2/ex_ALUData1_selector0_in_buffer\
+add wave -group "EX in buffers" -radix decimal sim:/PROCv2/ex_r1_in_buffer\
+-radix decimal sim:/PROCv2/ex_r2_in_buffer\
+-radix decimal sim:/PROCv2/ex_imm_in_buffer\
+-radix unsigned sim:/PROCv2/ex_dest_regadd_in_buffer\
+-radix alu sim:/PROCv2/ex_alu_op_in_buffer\
+-radix binary sim:/PROCv2/ex_ALUData1_selector0_in_buffer\
 sim:/PROCv2/ex_ALUData1_selector1_in_buffer\
 sim:/PROCv2/ex_ALUData2_selector0_in_buffer\
 sim:/PROCv2/ex_ALUData2_selector1_in_buffer\
@@ -54,45 +49,29 @@ sim:/PROCv2/ex_stall_in_buffer0\
 sim:/PROCv2/ex_byte_in_buffer\
 sim:/PROCv2/ex_WB_enable_in_buffer
 
-
-add wave -group "EX out signals" sim:/PROCv2/ex_ALU_result_out\
-sim:/PROCv2/ex_dest_regadd_out\
-sim:/PROCv2/ex_loaden_out\
+add wave -group "EX out signals" -radix decimal sim:/PROCv2/ex_ALU_result_out\
+-radix unsigned sim:/PROCv2/ex_dest_regadd_out\
+-radix binary sim:/PROCv2/ex_loaden_out\
 sim:/PROCv2/ex_storeen_out\
 sim:/PROCv2/ex_mem_data_out\
 sim:/PROCv2/ex_byte_out\
 sim:/PROCv2/ex_WB_enable_out
 
-add wave -group "MEM in buffers" sim:/PROCv2/mem_data_in_buffer\
-sim:/PROCv2/mem_address_in_buffer\
-sim:/PROCv2/mem_access_write_in_buffer\
+add wave -group "MEM in buffers" -radix decimal sim:/PROCv2/mem_data_in_buffer\
+-radix unsigned sim:/PROCv2/mem_address_in_buffer\
+-radix binary sim:/PROCv2/mem_access_write_in_buffer\
 sim:/PROCv2/mem_byte_in_buffer\
 sim:/PROCv2/mem_WB_enable_in_buffer\
-sim:/PROCv2/mem_WB_address_in_buffer
-
-
-add wave -group "MEM out signals" sim:/PROCv2/mem_WB_enable_out\
-sim:/PROCv2/mem_WB_address_out\
-sim:/PROCv2/mem_WB_data_out
-
-add wave -group "WB in buffers" sim:/PROCv2/wb_WB_enable_in_buffer\
-sim:/PROCv2/wb_WB_address_in_buffer\
-sim:/PROCv2/wb_WB_data_in_buffer
+-radix unsigned sim:/PROCv2/mem_WB_address_in_buffer
 
-add wave -group "EX" sim:/PROCv2/EXstage/sRS\
-sim:/PROCv2/EXstage/A1\
-sim:/PROCv2/EXstage/X1\
-sim:/PROCv2/EXstage/RSD\
-sim:/PROCv2/EXstage/sRT\
-sim:/PROCv2/EXstage/sRES\
-sim:/PROCv2/EXstage/arg2
 
-add wave -position end  sim:/procv2/EXstage/mux1/A
-add wave -position end  sim:/procv2/EXstage/mux1/X
-add wave -position end  sim:/procv2/EXstage/mux1/ctl
+add wave -group "MEM out signals" -radix binary sim:/PROCv2/mem_WB_enable_out\
+-radix unsigned sim:/PROCv2/mem_WB_address_out\
+-radix decimal sim:/PROCv2/mem_WB_data_out
 
-add wave -position 6  sim:/procv2/IDstage/branch_dest
-add wave -position 5  sim:/procv2/IDstage/branch_taken_internal
+add wave -group "WB in buffers" -radix binary sim:/PROCv2/wb_WB_enable_in_buffer\
+-radix unsigned sim:/PROCv2/wb_WB_address_in_buffer\
+-radix decimal sim:/PROCv2/wb_WB_data_in_buffer
 }
 ;
 

PROC/processor.tcl

@@ -0,0 +1,164 @@
+proc AddWaves {} {
+    ;#Add waves we're interested in to the Wave window
+
+add wave -group "Control Signals" sim:/PROCv2/clk\
+sim:/PROCv2/ex_reset\
+sim:/PROCv2/id_reset\
+sim:/PROCv2/if_reset\
+sim:/PROCv2/mem_reset
+
+add wave -group "IF in buffers" -radix unsigned sim:/PROCv2/if_pc_in_buffer\
+-radix binary sim:/PROCv2/if_pc_sel_in_buffer\
+-radix binary sim:/PROCv2/if_pc_enable_in_buffer
+
+add wave -group "IF out signals" -radix unsigned sim:/PROCv2/if_pc_out\
+-radix binary sim:/PROCv2/if_inst_out
+
+add wave -group "ID in buffers" -radix binary sim:/PROCv2/id_inst_in_buffer\
+sim:/PROCv2/id_wenable_in_buffer\
+-radix unsigned sim:/PROCv2/id_reg_add_in_buffer\
+-radix binary sim:/PROCv2/id_reg_data_in_buffer\
+-radix unsigned sim:/PROCv2/id_pc_in_buffer
+
+add wave -group "ID out signals" -radix unsigned sim:/PROCv2/id_pc_out\
+-radix alu sim:/PROCv2/id_alu_op_out\
+-radix decimal sim:/PROCv2/id_r1_out\
+-radix decimal sim:/PROCv2/id_r2_out\
+-radix decimal sim:/PROCv2/id_imm_out\
+-radix unsigned sim:/PROCv2/id_dest_regadd_out\
+-radix binary sim:/PROCv2/id_loaden_out\
+sim:/PROCv2/id_storeen_out\
+sim:/PROCv2/id_useimm_out\
+sim:/PROCv2/id_branch_out\
+sim:/PROCv2/id_byte_out\
+sim:/PROCv2/id_WB_enable_out
+
+add wave -group "EX in buffers" -radix decimal sim:/PROCv2/ex_r1_in_buffer\
+-radix decimal sim:/PROCv2/ex_r2_in_buffer\
+-radix decimal sim:/PROCv2/ex_imm_in_buffer\
+-radix unsigned sim:/PROCv2/ex_dest_regadd_in_buffer\
+-radix alu sim:/PROCv2/ex_alu_op_in_buffer\
+-radix binary sim:/PROCv2/ex_ALUData1_selector0_in_buffer\
+sim:/PROCv2/ex_ALUData1_selector1_in_buffer\
+sim:/PROCv2/ex_ALUData2_selector0_in_buffer\
+sim:/PROCv2/ex_ALUData2_selector1_in_buffer\
+sim:/PROCv2/ex_loaden_in_buffer\
+sim:/PROCv2/ex_storeen_in_buffer\
+sim:/PROCv2/ex_stall_in_buffer\
+sim:/PROCv2/ex_stall_in_buffer0\
+sim:/PROCv2/ex_byte_in_buffer\
+sim:/PROCv2/ex_WB_enable_in_buffer
+
+add wave -group "EX out signals" -radix decimal sim:/PROCv2/ex_ALU_result_out\
+-radix unsigned sim:/PROCv2/ex_dest_regadd_out\
+-radix binary sim:/PROCv2/ex_loaden_out\
+sim:/PROCv2/ex_storeen_out\
+sim:/PROCv2/ex_mem_data_out\
+sim:/PROCv2/ex_byte_out\
+sim:/PROCv2/ex_WB_enable_out
+
+add wave -group "MEM in buffers" -radix decimal sim:/PROCv2/mem_data_in_buffer\
+-radix unsigned sim:/PROCv2/mem_address_in_buffer\
+-radix binary sim:/PROCv2/mem_access_write_in_buffer\
+sim:/PROCv2/mem_byte_in_buffer\
+sim:/PROCv2/mem_WB_enable_in_buffer\
+-radix unsigned sim:/PROCv2/mem_WB_address_in_buffer
+
+
+add wave -group "MEM out signals" -radix binary sim:/PROCv2/mem_WB_enable_out\
+-radix unsigned sim:/PROCv2/mem_WB_address_out\
+-radix decimal sim:/PROCv2/mem_WB_data_out
+
+add wave -group "WB in buffers" -radix binary sim:/PROCv2/wb_WB_enable_in_buffer\
+-radix unsigned sim:/PROCv2/wb_WB_address_in_buffer\
+-radix decimal sim:/PROCv2/wb_WB_data_in_buffer
+}
+;
+
+proc runsim {} {
+      vsim PROCv2
+
+    AddWaves
+;#run 1 ns
+  force -deposit /PROCv2/if_pc_enable_in_buffer 0 0 ns
+  force -deposit /PROCv2/MEMstage/mem_access_write 0 0
+  force -deposit /PROCv2/MEMstage/data_in "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" 0
+  force -deposit /PROCv2/MEMstage/data_out "00000000000000000000000000000000" 0
+  force -deposit /PROCv2/MEMstage/address_in "00000000000000000000000000000000" 0
+  force -deposit /PROCv2/MEMstage/byte 0 0
+
+    GenerateCPUClock
+
+    force -deposit /PROCv2/reset 0 0
+
+
+  loadInstructions
+  run 1 ns
+  force -deposit /PROCv2/if_pc_in_buffer "00000000000000000000000000110000" 0
+  force -deposit /PROCv2/if_pc_enable_in_buffer 1 0 ns
+  force -deposit /PROCv2/reset 1 1
+    run 10 ns
+
+}
+
+proc loadInstructions {} {
+  force -deposit PROCv2/IFstage/instruction_memory/initialize 0 0 ns, 1 1 ns, 0 2 ns
+  ;#run 1 ns ;#Force signals to update right away
+}
+
+proc GenerateCPUClock {} {
+    force -deposit /PROCv2/clock 0 0 ns, 1 0.5 ns -repeat 1 ns
+}
+
+proc RadixDefine {} {
+    radix define alu {
+        4'b0000 "ADD",
+        4'b0001 "AND",
+        4'b0010 "DIV",
+        4'b0011 "EQUALS",
+        4'b0100 "LUI",
+        4'b0101 "MFHI",
+        4'b0110 "MFLO",
+        4'b0111 "MULT",
+        4'b1000 "NOR",
+        4'b1001 "OR",
+        4'b1010 "SLL",
+        4'b1011 "SLT",
+        4'b1100 "SRA",
+        4'b1101 "SRL",
+        4'b1110 "SUB",
+        4'b1111 "XOR"
+    }
+
+    radix define br_ctl {
+        2'b00 "NO",
+        2'b01 "EQ",
+        2'b10 "NE",
+        2'b11 "J"
+    }
+}
+
+
+proc Init {} {
+    vlib work
+
+    #Compile
+vcom Memory_in_Byte.vhd
+vcom memory_arbiter_lib.vhd
+vcom Main_Memory.vhd
+vcom memory_constants.vhd
+vcom Data_Mem.vhd
+vcom PC.vhd
+vcom MEM.vhd
+vcom fetch.vhd
+vcom shifter.vhd
+vcom comparator.vhd
+vcom Register.vhd
+vcom decode.vhd
+vcom ALU.vhd
+vcom mux41.vhd
+vcom EX.vhd
+vcom PROCv2.vhd
+
+RadixDefine
+}

README.md

@@ -5,7 +5,7 @@ Author:
  - Wei-Di Chang
  - David Lavoie-Boutin
  - Muhammad Ali Lashari
- - Sitara Sherrif
+ - Sitara Sheriff
 
 VHDL description of a 5-stage mips pipeline implementing early branch resolution, forwarding and hazard detection. This processor was implemented as a project deliverable for ECSE 425, Computer Organisation and Architecture.
 
@@ -97,8 +97,19 @@ Simply feed the proper signals from EX and MEM back to the register file in the
  1. Assemble the program to a binary file.
  2. Rename that compiled file to `Init.dat`
  3. Move that file in the project folder with the processor
- 4. Run the test script `processor.tcl`
+ 4. Source the test script `processor.tcl`
+ 5. Initialise the simulation with the command `Init`
+ 6. Run the simulation with the command `runsim`
+
 
 The script will load the instruction content in `Init.dat` inside the instruction memory, it will compile all the components and start the simulation. 
 
 **You might need to change the run duration to make sure you run the processor long enough.**
+
+The input and output of each stage are grouped together, with the clock in the control signal group.
+
+## Current Problems
+
+The secondairy branch `hazard_detection` implements the general mechanics for hazard detection, but thoroug testing has proven inconclusive for many tests. This will be corrected in the next release.
+
+The fibonachi program with integrated stalls will work for now as a replacement.