Add fixes to decode and stalled fibonacci sequence

Author: weidi-chang

PROC/Init.dat

@@ -1,24 +1,21 @@
-00000001010010110100100000100000
-00100000010000100000000010001010
-10001100111110010000000000010001
-00010010010000111111111111111101
-10101100100010000000000000100110
-00111100000111100001001110000010
-00000000010000110000100000100100
-00000001000000000000000000001000
-00000000111010010010000000100111
-00000001111100000111000000100101
-00000000000001000100000001000000
-00000000010000110000100000101010
-00000000000001010100000001000010
-00000001000000110111000000100010
-00000000000001000000000000011010
-00000000000000001101100000010010
-00000000000000001111000000010000
-00000001001100010000000000010100
-00000010000010010011100000100110
-00000000000001101001110111000011
-00100000100001100000000001110101
-00110000010000011111111111110110
-00010100011010001111111111110101
-10000000100100110000000000000000
+00100000000010100000000000000100
+00100000000000010000000000000001
+00100000000000100000000000000001
+00100000000010110000011111010000
+00100000000011110000000000000100
+00100000010000110000000000000000
+00100000000000000000000000000000
+00000000010000010001000000100000
+00100000011000010000000000000000
+00000001010011110000000000010100
+00000000000000000110000000010010
+00100000000000000000000000000000
+00100000000000000000000000000000
+00000001011011000110100000100000
+00100000000000000000000000000000
+00100000000000000000000000000000
+10101101101000100000000000000000
+00100001010010101111111111111111
+00010100000010101111111111110011
+00100000000000000000000000000000
+00010001011010110000000000000000

PROC/TEST2.tcl

@@ -33,6 +33,11 @@ sim:/PROCv2/id_branch_out\
 sim:/PROCv2/id_byte_out\
 sim:/PROCv2/id_WB_enable_out
 
+add wave -group "Comaprator signals" sim:/procv2/IDstage/reg_comparator/value1\
+sim:/procv2/IDstage/reg_comparator/value2\
+sim:/procv2/IDstage/reg_comparator/ctl\
+sim:/procv2/IDstage/reg_comparator/taken
+
 add wave -group "EX in buffers" sim:/PROCv2/ex_r1_in_buffer\
 sim:/PROCv2/ex_r2_in_buffer\
 sim:/PROCv2/ex_imm_in_buffer\
@@ -86,7 +91,8 @@ add wave -position end  sim:/procv2/EXstage/mux1/A
 add wave -position end  sim:/procv2/EXstage/mux1/X
 add wave -position end  sim:/procv2/EXstage/mux1/ctl
 
-
+add wave -position 6  sim:/procv2/IDstage/branch_dest
+add wave -position 5  sim:/procv2/IDstage/branch_taken_internal
 }
 ;
 

PROC/decode.vhd

@@ -291,8 +291,8 @@ begin
                     branch_ctl <= "01";
                     use_imm <= '0';
                     immediate_out_internal <=  To_StdLogicVector(to_bitvector(std_logic_vector(resize(signed(instruction_in(15 downto 0)), immediate_out_internal'length))) sll 2);
-                    r1 <= (others => '0');
-                    r2 <= (others => '0');
+                    -- r1 <= (others => '0');
+                    -- r2 <= (others => '0');
                     write_back_enable <= '0';
 
                 when "000101" =>
@@ -301,8 +301,8 @@ begin
                     use_imm <= '0';
                     branch_ctl <= "10";
                     immediate_out_internal <=  To_StdLogicVector(to_bitvector(std_logic_vector(resize(signed(instruction_in(15 downto 0)), immediate_out_internal'length))) sll 2);
-                    r1 <= (others => '0');
-                    r2 <= (others => '0');
+                    -- r1 <= (others => '0');
+                    -- r2 <= (others => '0');
                     write_back_enable <= '0';
 
                 when others =>
@@ -315,7 +315,7 @@ begin
     immediate_out <= immediate_out_internal;
     reg1_out <= reg1_out_internal;
     reg2_out <= reg2_out_internal;
-    
+
     reg1_addr <= r1;
     reg2_addr <= r2;
 

PROC/fib.asm

@@ -0,0 +1,28 @@
+###############################################
+# This program generates Fibonacci series.
+# It stores the generated Fibonacci numbers fisrt into, Reg[2] ($2), and then into memory
+# Assume that your data section in memory starts from address 2000
+
+	addi $10,  $0, 4	# number of generating Fibonacci-numbers
+	addi $1,   $0, 1	# initializing Fib(-1) = 0
+	addi $2,   $0, 1	# initializing Fib(0) = 1
+	addi $11,  $0, 2000  	# initializing the beginning of Data Section address in memory
+	addi $15,  $0, 4	# word size in byte
+
+loop:	addi $3, $2, 0		# temp = Fib(n-1)
+  addi $0, $0, 0
+	add  $2, $2, $1		# Fib(n)=Fib(n-1)+Fib(n-2)
+	addi $1, $3, 0		# Fib(n-2)=temp=Fib(n-1)
+	mult $10, $15		# $lo=4*$10, for word alignment
+	mflo $12		# assume small numbers
+  addi $0, $0, 0
+  addi $0, $0, 0
+	add  $13, $11, $12	# Make data pointer [2000+($10)*4]
+  addi $0, $0, 0
+  addi $0, $0, 0
+	sw	 $2, 0($13)	# Mem[$10+2000] <-- Fib(n)
+	addi $10, $10, -1	# loop index
+	bne  $10, $0, loop
+  addi $0, $0, 0
+EoP:	beq	 $11, $11, EoP 	#end of program (infinite loop)
+###############################################