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Winch: Add SIMD comparison instructions for x64 with AVX (bytecodealliance#10148)
* Winch: Add SIMD comparison instructions for x64 with AVX * Move passing test out of unsupported list
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55 files changed

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‎crates/wast-util/src/lib.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -425,44 +425,37 @@ impl WastTest {
425425
"misc_testsuite/simd/almost-extmul.wast",
426426
"misc_testsuite/simd/canonicalize-nan.wast",
427427
"misc_testsuite/simd/cvt-from-uint.wast",
428-
"misc_testsuite/simd/issue6725-no-egraph-panic.wast",
429428
"misc_testsuite/simd/issue_3327_bnot_lowering.wast",
430429
"spec_testsuite/simd_bit_shift.wast",
431430
"spec_testsuite/simd_boolean.wast",
432431
"spec_testsuite/simd_const.wast",
433432
"spec_testsuite/simd_conversions.wast",
434433
"spec_testsuite/simd_f32x4.wast",
435434
"spec_testsuite/simd_f32x4_arith.wast",
436-
"spec_testsuite/simd_f32x4_cmp.wast",
437435
"spec_testsuite/simd_f32x4_pmin_pmax.wast",
438436
"spec_testsuite/simd_f32x4_rounding.wast",
439437
"spec_testsuite/simd_f64x2.wast",
440438
"spec_testsuite/simd_f64x2_arith.wast",
441-
"spec_testsuite/simd_f64x2_cmp.wast",
442439
"spec_testsuite/simd_f64x2_pmin_pmax.wast",
443440
"spec_testsuite/simd_f64x2_rounding.wast",
444441
"spec_testsuite/simd_i16x8_arith.wast",
445442
"spec_testsuite/simd_i16x8_arith2.wast",
446-
"spec_testsuite/simd_i16x8_cmp.wast",
447443
"spec_testsuite/simd_i16x8_extadd_pairwise_i8x16.wast",
448444
"spec_testsuite/simd_i16x8_extmul_i8x16.wast",
449445
"spec_testsuite/simd_i16x8_q15mulr_sat_s.wast",
450446
"spec_testsuite/simd_i16x8_sat_arith.wast",
451447
"spec_testsuite/simd_i32x4_arith.wast",
452448
"spec_testsuite/simd_i32x4_arith2.wast",
453-
"spec_testsuite/simd_i32x4_cmp.wast",
454449
"spec_testsuite/simd_i32x4_dot_i16x8.wast",
455450
"spec_testsuite/simd_i32x4_extadd_pairwise_i16x8.wast",
456451
"spec_testsuite/simd_i32x4_extmul_i16x8.wast",
457452
"spec_testsuite/simd_i32x4_trunc_sat_f32x4.wast",
458453
"spec_testsuite/simd_i32x4_trunc_sat_f64x2.wast",
459454
"spec_testsuite/simd_i64x2_arith.wast",
460455
"spec_testsuite/simd_i64x2_arith2.wast",
461-
"spec_testsuite/simd_i64x2_cmp.wast",
462456
"spec_testsuite/simd_i64x2_extmul_i32x4.wast",
463457
"spec_testsuite/simd_i8x16_arith.wast",
464458
"spec_testsuite/simd_i8x16_arith2.wast",
465-
"spec_testsuite/simd_i8x16_cmp.wast",
466459
"spec_testsuite/simd_i8x16_sat_arith.wast",
467460
"spec_testsuite/simd_int_to_int_extend.wast",
468461
"spec_testsuite/simd_lane.wast",
@@ -479,11 +472,18 @@ impl WastTest {
479472
#[cfg(target_arch = "x86_64")]
480473
if !(std::is_x86_feature_detected!("avx") && std::is_x86_feature_detected!("avx2")) {
481474
let unsupported = [
475+
"misc_testsuite/simd/issue6725-no-egraph-panic.wast",
482476
"misc_testsuite/simd/replace-lane-preserve.wast",
483477
"misc_testsuite/simd/spillslot-size-fuzzbug.wast",
484478
"misc_testsuite/winch/_simd_lane.wast",
485479
"misc_testsuite/winch/_simd_splat.wast",
486480
"spec_testsuite/simd_align.wast",
481+
"spec_testsuite/simd_f32x4_cmp.wast",
482+
"spec_testsuite/simd_f64x2_cmp.wast",
483+
"spec_testsuite/simd_i16x8_cmp.wast",
484+
"spec_testsuite/simd_i32x4_cmp.wast",
485+
"spec_testsuite/simd_i64x2_cmp.wast",
486+
"spec_testsuite/simd_i8x16_cmp.wast",
487487
"spec_testsuite/simd_load_extend.wast",
488488
"spec_testsuite/simd_load_splat.wast",
489489
"spec_testsuite/simd_store16_lane.wast",

‎tests/disas/winch/x64/f32x4_eq/const_avx.wat

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (result v128)
7+
(f32x4.eq (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3))
8+
)
9+
)
10+
;; wasm[0]::function[0]:
11+
;; pushq %rbp
12+
;; movq %rsp, %rbp
13+
;; movq 8(%rdi), %r11
14+
;; movq 0x10(%r11), %r11
15+
;; addq $0x10, %r11
16+
;; cmpq %rsp, %r11
17+
;; ja 0x4b
18+
;; 1c: movq %rdi, %r14
19+
;; subq $0x10, %rsp
20+
;; movq %rdi, 8(%rsp)
21+
;; movq %rsi, (%rsp)
22+
;; movdqu 0x1c(%rip), %xmm0
23+
;; movdqu 0x24(%rip), %xmm1
24+
;; vcmpeqps %xmm0, %xmm1, %xmm1
25+
;; movdqa %xmm1, %xmm0
26+
;; addq $0x10, %rsp
27+
;; popq %rbp
28+
;; retq
29+
;; 4b: ud2
30+
;; 4d: addb %al, (%rax)
31+
;; 4f: addb %al, (%rax)
32+
;; 51: addb %al, (%rax)
33+
;; 53: addb %al, (%rax)
34+
;; 55: addb %al, 0x3f(%rax)
35+
;; 5b: addb %al, (%rax)
36+
;; 5e: addb %al, (%rax)
37+
;; 62: addb %al, (%rax)
38+
;; 66: addb %al, (%rax)
39+
;; 69: addb %al, 0x3f(%rax)

‎tests/disas/winch/x64/f32x4_ge/const_avx.wat

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (result v128)
7+
(f32x4.ge (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3))
8+
)
9+
)
10+
;; wasm[0]::function[0]:
11+
;; pushq %rbp
12+
;; movq %rsp, %rbp
13+
;; movq 8(%rdi), %r11
14+
;; movq 0x10(%r11), %r11
15+
;; addq $0x10, %r11
16+
;; cmpq %rsp, %r11
17+
;; ja 0x4b
18+
;; 1c: movq %rdi, %r14
19+
;; subq $0x10, %rsp
20+
;; movq %rdi, 8(%rsp)
21+
;; movq %rsi, (%rsp)
22+
;; movdqu 0x1c(%rip), %xmm0
23+
;; movdqu 0x24(%rip), %xmm1
24+
;; vcmpleps %xmm1, %xmm0, %xmm1
25+
;; movdqa %xmm1, %xmm0
26+
;; addq $0x10, %rsp
27+
;; popq %rbp
28+
;; retq
29+
;; 4b: ud2
30+
;; 4d: addb %al, (%rax)
31+
;; 4f: addb %al, (%rax)
32+
;; 51: addb %al, (%rax)
33+
;; 53: addb %al, (%rax)
34+
;; 55: addb %al, 0x3f(%rax)
35+
;; 5b: addb %al, (%rax)
36+
;; 5e: addb %al, (%rax)
37+
;; 62: addb %al, (%rax)
38+
;; 66: addb %al, (%rax)
39+
;; 69: addb %al, 0x3f(%rax)

‎tests/disas/winch/x64/f32x4_gt/const_avx.wat

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (result v128)
7+
(f32x4.gt (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3))
8+
)
9+
)
10+
;; wasm[0]::function[0]:
11+
;; pushq %rbp
12+
;; movq %rsp, %rbp
13+
;; movq 8(%rdi), %r11
14+
;; movq 0x10(%r11), %r11
15+
;; addq $0x10, %r11
16+
;; cmpq %rsp, %r11
17+
;; ja 0x4b
18+
;; 1c: movq %rdi, %r14
19+
;; subq $0x10, %rsp
20+
;; movq %rdi, 8(%rsp)
21+
;; movq %rsi, (%rsp)
22+
;; movdqu 0x1c(%rip), %xmm0
23+
;; movdqu 0x24(%rip), %xmm1
24+
;; vcmpltps %xmm1, %xmm0, %xmm1
25+
;; movdqa %xmm1, %xmm0
26+
;; addq $0x10, %rsp
27+
;; popq %rbp
28+
;; retq
29+
;; 4b: ud2
30+
;; 4d: addb %al, (%rax)
31+
;; 4f: addb %al, (%rax)
32+
;; 51: addb %al, (%rax)
33+
;; 53: addb %al, (%rax)
34+
;; 55: addb %al, 0x3f(%rax)
35+
;; 5b: addb %al, (%rax)
36+
;; 5e: addb %al, (%rax)
37+
;; 62: addb %al, (%rax)
38+
;; 66: addb %al, (%rax)
39+
;; 69: addb %al, 0x3f(%rax)

‎tests/disas/winch/x64/f32x4_le/const_avx.wat

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (result v128)
7+
(f32x4.le (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3))
8+
)
9+
)
10+
;; wasm[0]::function[0]:
11+
;; pushq %rbp
12+
;; movq %rsp, %rbp
13+
;; movq 8(%rdi), %r11
14+
;; movq 0x10(%r11), %r11
15+
;; addq $0x10, %r11
16+
;; cmpq %rsp, %r11
17+
;; ja 0x4b
18+
;; 1c: movq %rdi, %r14
19+
;; subq $0x10, %rsp
20+
;; movq %rdi, 8(%rsp)
21+
;; movq %rsi, (%rsp)
22+
;; movdqu 0x1c(%rip), %xmm0
23+
;; movdqu 0x24(%rip), %xmm1
24+
;; vcmpleps %xmm0, %xmm1, %xmm1
25+
;; movdqa %xmm1, %xmm0
26+
;; addq $0x10, %rsp
27+
;; popq %rbp
28+
;; retq
29+
;; 4b: ud2
30+
;; 4d: addb %al, (%rax)
31+
;; 4f: addb %al, (%rax)
32+
;; 51: addb %al, (%rax)
33+
;; 53: addb %al, (%rax)
34+
;; 55: addb %al, 0x3f(%rax)
35+
;; 5b: addb %al, (%rax)
36+
;; 5e: addb %al, (%rax)
37+
;; 62: addb %al, (%rax)
38+
;; 66: addb %al, (%rax)
39+
;; 69: addb %al, 0x3f(%rax)

‎tests/disas/winch/x64/f32x4_lt/const_avx.wat

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (result v128)
7+
(f32x4.lt (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3))
8+
)
9+
)
10+
;; wasm[0]::function[0]:
11+
;; pushq %rbp
12+
;; movq %rsp, %rbp
13+
;; movq 8(%rdi), %r11
14+
;; movq 0x10(%r11), %r11
15+
;; addq $0x10, %r11
16+
;; cmpq %rsp, %r11
17+
;; ja 0x4b
18+
;; 1c: movq %rdi, %r14
19+
;; subq $0x10, %rsp
20+
;; movq %rdi, 8(%rsp)
21+
;; movq %rsi, (%rsp)
22+
;; movdqu 0x1c(%rip), %xmm0
23+
;; movdqu 0x24(%rip), %xmm1
24+
;; vcmpltps %xmm0, %xmm1, %xmm1
25+
;; movdqa %xmm1, %xmm0
26+
;; addq $0x10, %rsp
27+
;; popq %rbp
28+
;; retq
29+
;; 4b: ud2
30+
;; 4d: addb %al, (%rax)
31+
;; 4f: addb %al, (%rax)
32+
;; 51: addb %al, (%rax)
33+
;; 53: addb %al, (%rax)
34+
;; 55: addb %al, 0x3f(%rax)
35+
;; 5b: addb %al, (%rax)
36+
;; 5e: addb %al, (%rax)
37+
;; 62: addb %al, (%rax)
38+
;; 66: addb %al, (%rax)
39+
;; 69: addb %al, 0x3f(%rax)

‎tests/disas/winch/x64/f32x4_ne/const_avx.wat

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (result v128)
7+
(f32x4.ne (v128.const f32x4 3 2 1 0) (v128.const f32x4 0 1 2 3))
8+
)
9+
)
10+
;; wasm[0]::function[0]:
11+
;; pushq %rbp
12+
;; movq %rsp, %rbp
13+
;; movq 8(%rdi), %r11
14+
;; movq 0x10(%r11), %r11
15+
;; addq $0x10, %r11
16+
;; cmpq %rsp, %r11
17+
;; ja 0x4b
18+
;; 1c: movq %rdi, %r14
19+
;; subq $0x10, %rsp
20+
;; movq %rdi, 8(%rsp)
21+
;; movq %rsi, (%rsp)
22+
;; movdqu 0x1c(%rip), %xmm0
23+
;; movdqu 0x24(%rip), %xmm1
24+
;; vcmpneqps %xmm0, %xmm1, %xmm1
25+
;; movdqa %xmm1, %xmm0
26+
;; addq $0x10, %rsp
27+
;; popq %rbp
28+
;; retq
29+
;; 4b: ud2
30+
;; 4d: addb %al, (%rax)
31+
;; 4f: addb %al, (%rax)
32+
;; 51: addb %al, (%rax)
33+
;; 53: addb %al, (%rax)
34+
;; 55: addb %al, 0x3f(%rax)
35+
;; 5b: addb %al, (%rax)
36+
;; 5e: addb %al, (%rax)
37+
;; 62: addb %al, (%rax)
38+
;; 66: addb %al, (%rax)
39+
;; 69: addb %al, 0x3f(%rax)

‎tests/disas/winch/x64/f64x2_eq/const_avx.wat

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (result v128)
7+
(f64x2.eq (v128.const i64x2 1 0) (v128.const i64x2 0 1))
8+
)
9+
)
10+
;; wasm[0]::function[0]:
11+
;; pushq %rbp
12+
;; movq %rsp, %rbp
13+
;; movq 8(%rdi), %r11
14+
;; movq 0x10(%r11), %r11
15+
;; addq $0x10, %r11
16+
;; cmpq %rsp, %r11
17+
;; ja 0x4b
18+
;; 1c: movq %rdi, %r14
19+
;; subq $0x10, %rsp
20+
;; movq %rdi, 8(%rsp)
21+
;; movq %rsi, (%rsp)
22+
;; movdqu 0x1c(%rip), %xmm0
23+
;; movdqu 0x24(%rip), %xmm1
24+
;; vcmpeqpd %xmm0, %xmm1, %xmm1
25+
;; movdqa %xmm1, %xmm0
26+
;; addq $0x10, %rsp
27+
;; popq %rbp
28+
;; retq
29+
;; 4b: ud2
30+
;; 4d: addb %al, (%rax)
31+
;; 4f: addb %al, (%rax)
32+
;; 51: addb %al, (%rax)
33+
;; 53: addb %al, (%rax)
34+
;; 55: addb %al, (%rax)
35+
;; 57: addb %al, (%rcx)
36+
;; 59: addb %al, (%rax)
37+
;; 5b: addb %al, (%rax)
38+
;; 5d: addb %al, (%rax)
39+
;; 5f: addb %al, (%rcx)
40+
;; 61: addb %al, (%rax)
41+
;; 63: addb %al, (%rax)
42+
;; 65: addb %al, (%rax)
43+
;; 67: addb %al, (%rax)
44+
;; 69: addb %al, (%rax)
45+
;; 6b: addb %al, (%rax)
46+
;; 6d: addb %al, (%rax)

‎tests/disas/winch/x64/f64x2_ge/const_avx.wat

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (result v128)
7+
(f64x2.ge (v128.const i64x2 1 0) (v128.const i64x2 0 1))
8+
)
9+
)
10+
;; wasm[0]::function[0]:
11+
;; pushq %rbp
12+
;; movq %rsp, %rbp
13+
;; movq 8(%rdi), %r11
14+
;; movq 0x10(%r11), %r11
15+
;; addq $0x10, %r11
16+
;; cmpq %rsp, %r11
17+
;; ja 0x4b
18+
;; 1c: movq %rdi, %r14
19+
;; subq $0x10, %rsp
20+
;; movq %rdi, 8(%rsp)
21+
;; movq %rsi, (%rsp)
22+
;; movdqu 0x1c(%rip), %xmm0
23+
;; movdqu 0x24(%rip), %xmm1
24+
;; vcmplepd %xmm1, %xmm0, %xmm1
25+
;; movdqa %xmm1, %xmm0
26+
;; addq $0x10, %rsp
27+
;; popq %rbp
28+
;; retq
29+
;; 4b: ud2
30+
;; 4d: addb %al, (%rax)
31+
;; 4f: addb %al, (%rax)
32+
;; 51: addb %al, (%rax)
33+
;; 53: addb %al, (%rax)
34+
;; 55: addb %al, (%rax)
35+
;; 57: addb %al, (%rcx)
36+
;; 59: addb %al, (%rax)
37+
;; 5b: addb %al, (%rax)
38+
;; 5d: addb %al, (%rax)
39+
;; 5f: addb %al, (%rcx)
40+
;; 61: addb %al, (%rax)
41+
;; 63: addb %al, (%rax)
42+
;; 65: addb %al, (%rax)
43+
;; 67: addb %al, (%rax)
44+
;; 69: addb %al, (%rax)
45+
;; 6b: addb %al, (%rax)
46+
;; 6d: addb %al, (%rax)

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