[Session 2] PyAIE: A Python-based Programming Framework for Versal ACAP AI Engines

[zsisco]

Authors: Hongzheng Tian, Shining Yang, Yoonha Cha, Sitao Huang (University of California, Irvine)
https://capra.cs.cornell.edu/latte23/paper/10.pdf

[sampsyo]

I think the AIE is a super exciting addition the FPGA landscape! I know this is outside the scope of the paper, but I would be really interested to hear if the authors have thoughts about what is still unsolved in the realm of AIE compilation.

[hongzhengTian]

Thank you for your interest in our project. At present, except for the Vitis from Xilinx, there are not many third-party compilers for the AIE, or Versal ACAP platform. In order to improve productivity, we hope that the programming of Versal ACAP can be implemented faster, and the performance can match or even exceed the effect of manual programming. An ideal AIE compiler should be able to compile high-level code into C/C++ code that conforms to the Versal ACAP specification, and provide corresponding optimizations, such as automatically adopting a more reasonable memory hierarchy, faster communication between AIE tiles, and allocating AIE resources more reasonably for different functions, and more efficient function scheduling on the host side. These requirements are all currently unresolved issues in the field of AIE compilation.

[uv-xiao]

It looks like there's a whole lot of potential here, especially when it comes to that optimization section. It's clear that AIE kernel programming comes with some additional constraints and options, such as limited registers, memories, and processing units inside one AIE tile. And actually, CHARM completes the kernel programming manually. Now, the real question is: can PyAIE take these constraints into consideration for optimization? Sounds like an interesting challenge.

[hongzhengTian]

Thank you for your question! As you pointed out, this is very interesting and challenging work.
This is an ongoing project, and many features are remaining to be added. Currently, we only consider the constraints of the number of AIE tiles, communication interfaces between PL and AIE, and the buffer size and on-board memory size. What you mentioned is part of our plan for future work. Because in our current testbench, the function that runs on a single AIE is small and hasn't reached out to the constraints of one single AIE.