[Session 2] Exploring Performance of Cache-Aware Tiling Strategies in MLIR Infrastructure

[zsisco]

Authors: Mingyu Chen, Yu Zhang (Advanced-tech campus of University of Science and Technology of China, Hefei, Anhui Province, China); Hongbo Rong, Jianhui Li (Intel)
https://capra.cs.cornell.edu/latte23/paper/7.pdf

[sampsyo]

These were some very interesting empirical results! There is an age-old problem here about understanding the performance gap between compiled and hand-tuned code (where oneDNN is representative of the latter). Here's one experiment that could be really interesting to do: for a specific point in the design space, manually try to optimize the result of MLIR compilation to match the performance of OneDNN. Record the optimizations required to bridge the gap. Then, these transformations could become "grist for the mill" in improving the MLIR compilation pipeline.