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paypal.me/briansune
Please visit FPGA-TFT-MIPI-or-DPI or FPGA-LCD-MIPI-or-DPI
In the past, many Xilinx FPGA developers and users wanted to utilize the "MIPI DSI TX Controller Subsystem" IP.
Unfortunately, due to the absence of LPDT, users were unable to initialize the LCD/TFT display. Hence, the usefulness of this built-in Vivado IP was highly limited.
In this project, a novel, ultra-low-resource, Verilog-based HDL design has been developed to address this niche need.
This design requires neither a softcore nor a hardcore (using only pure FSM + LUT), significantly reducing complexity.
Additionally, the design is independent of Vivado IP (excluding inherent FPGA building blocks) and does not require a DPHY IP either.
Remarks: R61322 driver IC is very puzzling on the DSC and Generic Command via LPDT.
To enable a normal non-burst mode video, "29" and "11" is sent via HS rather than LPDT. Such result is repeatable under SSD2828 bridge IC.
However, when using Generic-Command with LPDT "11" and "29" on SSD2828 bridge it is able to trigger a normal video mode.
Which such procedure is unable to repeat on FPGA setup.
| BPP,FPS,FPGA,Lanes,I/F | Video |
|---|---|
| 24, 60,K7,4, R-Net |  |
| 24, 60,K7,4,R-Net Flip |  |
| 24, 60,K7,4, IC |  |
| 24,~20,K7,2, IC |  |
| 24,~20,ZU,2, FPGA |  |
Please contact via EMAIL: briansune@gmail.com
- Modify the Python script and convert the initialization LPDT ROM (read-only-memory)
- Make sure the hardware is MIPI DSI supported. Xilinx FPGA please check HERE or Altera FPGA please check HERE
- Make sure the MMCM and parameters are converged
- Ensure the MIPI Mbps is lower than 900, which is tested on the 5.0 inch 1080p TFT 60 FPS.
| Description | EVM |
|---|---|
| FPGA K7-IC |  |
| FPGA K7-R-Net |  |
| FPGA K7-R-Net |  |
| FPGA ZU |  |
| 5" LCD |  |
Remarks A: From the above experiments and implementations, there are no major differences on MC20902 and resistor-network.
Remarks B: The different between resistor-network and level-shifter is w/ or w/o tri-state on the FPGA out-buffer.
| BPP,FPS,FPGA,Lanes,I/F | Resources |
|---|---|
| 24,60,K7,4,R-Net |  |
| 24,60,K7,4,Level-Shifter |  |
| 24,~20,K7,2,Level-Shifter |  |
| 24,~20,ZU,2,FPGA-MIPI-IO |  |
Remarks 1: Ultrascale+ devices and 7 series have different serialization building blocks.
Remarks 2: Ultrascale+ devices have MIPI physical interface, which no extra resistor-network or front-end ICs are needed.
Remarks 3: The only Verilog design that are changed to cope with Ultrascale+ device are the serialization and MMCM blocks.
|-mipi_init_script
| |-main.py
| |-mipi_setup_rom.mem
| |-one_lane_lcd.txt
|-mipi_phys
| |-mipi_crc.v
| |-mipi_ecc.v
| |-mipi_hs_clk_phy.v
| |-mipi_hs_phy.v
| |-mipi_lps_phy.v
|-mipi_refclks
| |-mipi_refclks.v
|-mipi_setup
| |-mipi_lpdt_setup.v
| |-mipi_reset.v
| |-mipi_setup_rom.mem
|-mipi_sim
| |-tb_mipi_setup.v
| |-tb_mipi_top.v
| |-tb_mipi_video.v
|-mipi_top.v
|-top.xdc
|-video_src
| |-mipi_long_vid_pack.v
| |-mipi_remap.v
| |-mipi_short_vid_hdr.v
| |-mipi_video_stream.v
| |-test_pattern_gen.v
| |-video_timing_ctrl.v