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LATENTRED
Andrew Zonenberg edited this page Sep 9, 2018
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LATENTRED is a 1U layer-2 Ethernet switch.
Ports:
- 24x 10/100/1000 base-T, using TI DP83867 SGMII PHY
- 4x 10Gbase-R SFP+
- 1x 10/100/1000 base-T dedicated management port (management not possible from normal fabric interfaces)
- RS-232 UART console using Cisco-style RJ45 connector
Block-level overview:
- Power supply (TBD).
- COTS module of some sort
- 120V mains to 12V DC 5A (expected actual power usage is under 50W worst case)
- TODO: 48V DC input option
- Main board (Multech 6-8 layer)
- FPGA: Xilinx Kintex-7, -2 speed grade, FBG484 package. Gate capacity TBD.
- Management / IO expander card: INTEGRALSTICK (FIXME link here)
- SFP+ interfaces
- Management PHY / console connector
- Backplane (OSHPark 4-layer)
- Connect to main board and line cards via Samtec Q-strip (QTH-040-xx-DP)
- Possibly use DS25BR440TSQX (LVDS buffer) or DS110DF410SQ (LVDS retimer) if we have issues with SI
- First spin will be entirely passive
- 8x 1000base-T line card (OSHPark 4-layer)
- 3 cards, 8 PHYs each
- Backplane connection
- 8x SGMII
- 5V power (4 pins each power/ground)
- Lots of signal grounds
- MDIO
- I2C
- Hardware reset (broadcast to all PHYs)
- Power-good output?
- Tentative: 8x 1000base-X line card (OSHPark 4-layer)
- 8 SFP ports per card, using DS110DF410SQ to clean up signal from FPGA IO pins
- 802.1q
- 802.3ad?