Improve VPCLMULQDQ to use 512-bit wide registers #8
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When using 512-bit registers, we need to use coefficient pairs for folding 256 byte distances, as opposed to the 128 byte folding differences for smaller registers.
Only for x86_64 CPUs supporting VPCLMULQD. Gated behind builds using +nightly with the “vpclmulqdq” feature flag. Provides nearly a 2X boost in throughput. CRC-64/NVME is now ~96GiB/s on Intel Sapphire Rapids (AWS EC2 c7i.metal-48xl), up from ~56GiB/s.
Represents the new performance impact from the wider AVX512 registers.
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The Problem
The current implementation uses 4 x 256-bit registers, but modern VPCLMULQDQ CPUs support 512-bit operations, which should be faster.
The Solution
Implement 4 x 512-bit operations for increased throughput. CRC-64/NVME calculations went from ~56.4 GiB/s to ~96.1 GiB/s on a Sapphire Rapids AWS EC c7i.8xlarge instance.
Changes
Planned version bump
MINORnightlyand thevpclmulqdqfeature flag)