This project is aimed to demomnstrate my understanding of digital systems, VHDL skills, modular design.
A broad overview of the project can be seen below. For a detail, description please check out the full report (in french) the pdf file called
Conception avancée des systèmes informatique.
I implemented reduced instruction set computer with pipe-lining using VHDL.
There is an added hazard correction capabilities that can flush out parts of the processor and create a gap in the pipeline
I have created a timing diagram for every module to ensure correct functionality using ModelSim software and tested it on an FPGA
