rv32i cycle accurate model

This project was a comprehensive and extensive creation and implementation of 40 instructions on the Reduced Instruction Set Computer (RISC-V) architecture, where I designed and debugged complete CPU functionality from the ground up. Each instruction required specific pipelining which was modified throughout the project, demanding meticulous attention to detail in handling data hazards, control hazards, and forwarding mechanisms. Among each phase came different levels of complications, intricacy, knowledge, and patience, particularly when implementing complex instructions like branching and memory operations (loading and storing). The project helped provide an in-depth understanding of how a RISC-V-based CPU would progress throughout each clock cycle, including crucial concepts like instruction fetch, decode, execute, memory access, and write-back stages. The RISC-V architecture's multi-stage-pipelined nature required careful consideration of timing constraints and dependencies between instructions, giving me hands-on experience with real-world CPU design challenges. This project not only enhanced my technical skills in hardware description languages and digital design but also developed my problem-solving abilities and resilience when faced with complex system-level challenges.