M2k: prepare for alpha - v0.15
Submodule linux e4025f7..05dd68f:
> drivers/iio/logic/m2k-fabric: Fix warning use cansleep variant
> dts/zynq-m2k-rev[a|b].dts: m2k-fabric: Keep AMPs in powerdown after boot
> iio/logic/m2k-fabric.c: Add clk_powerdown support
> iio/logic/m2k-fabric: Add dt option to stay in PowerDown after boot
> drivers/clk/clk-adf4360: Add PowerDown support
Submodule buildroot 6a099c7..628b56c:
> configs/zynq_m2k_defconfig: check BR2_PACKAGE_LIBIIO
> Merge branch 'pluto' of https://github.com/analogdevicesinc/buildroot into pluto
> board/m2k/S16xadc: Keep XADC around for now
> board/m2k/S21misc: PowerDown M2K clocks after boot
> board/pluto/S23udc: Add ad9361-phy,xo_correction context attribute
> configs/zynq_m2k_defconfig: Add LIBIIO_IIOD_USBD
> configs/zynq_pluto_defconfig: Add LIBIIO_IIOD_USBD
> package/expat/expat: Downgrade to version 2.2.0
> Revert "skeleton: fix permissions on /dev/pts/ptmx"
> Merge remote-tracking branch 'origin/pluto' into test
> Merge tag '2017.05.1' into test
Submodule hdl 99e8aa3..c1e990b:
> ad9361/sw- current sw requires clock edge swap
> adrv9364- ps_intr_11 used for pps
> library/ad9361- gps_pps default value
> projects/ remove upack dma_xfer_in
> library/ad9361- add pps module
> hdlmake.pl updates
> adrv9361x/- ps_intr_11 used for pps
> daq3/zcu102: Initial commit
> daq1_zed: Initial commit
> arradio- remove dma_xfer_in from upack
> rfifo/upack- changes
> util_upack- port updates
> ad_mem- syntax error fix
> util_rfifo- add valid turnaround
> util_upack- add valid turnaround
> Remove executable flag from non-executable files
> avl_adxcvr: Derive PLL and core clock frequency from lane rate
> avl_adxcvr: Fix core clock bridge frequency
> common: a10soc: Set IO standard for differential signal negative side
> common: a10soc: Fix gpio_bd_i constraints
> license: Update old license headers
> adrv9364z7020: Connect the gps_pps signal to the receiver
> adrv9361z7035: Connect the gps_pps signal to the receiver
> axi_ad9361: ad_pps_receiver integration
> ad_pps_receiver: Initial commit
> A10GX: Update DDR3 configuration
> jesd204: axi_jesd204_rx_regmap_tb: Check ILAS memory register
> hdlmake.pl- remove ad_lvds
> library & projects- ad_lvds/ad_data replace
> library- remove ad_cmos_*
> ad77681evb/zed: ad_lvds-ad_data replace
> ad9361/xilinx/lvds_if- fix frame check
> library/xilinx/common- add iodelay group
> hdlmake.pl/fmcomms2- updates
> axi_ad9361- altera/xilinx reconcile- may be broken- do not use
> library/xilinx- lvds/cmos integration
> fmcomms2_kcu105: Initial commit
> axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains
> axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters
> avl_adxcfg: Consistently use non-blocking assignments
> library: Use ad_ip_intf_s_axi were applicable
> adi_ip_alt.tcl: ad_ip_intf_s_axi: Allow to specify AXI interface address width
> altera: axi_adxcvr: Reduce register map interface address width
> hdlmake.pl updates
> axi_ad9361/altera- add 10 support
> ad9361/xilinx- missing up_rstn
> Partially revert "hdlmake.pl - updates"
> axi_dac_interpolate: Added matlab file for interpolation filters
> axi_adc_decimate: Added matlab file for filters
> ZCU102: SPI assign chip selects individually
> hdlmake.pl - updates
> arradio- timing violations fix
> altera- remove lvds/serdes/cmos cores
> alt_serdes- remove c5 support
> library- remove c5 cores
> hdl/library- fix syntax errors/synthesis warnings
> common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion
> up_clock_mon: Explicitly truncate d_count during up_d_count assignment
> jesd204: jesd204_up_common: Rename clock monitor instance to i_clock_mon
> jesd204: jesd204_up_ilas_mem: Fix blocking assignment
> axi_dmac: axi_dmac_hw.tcl: Set read and write issuing capabilities
> axi_dmac: axi_dmac_hw.tcl: Set default DMA_LENGTH_WIDTH to 24
> arradio/c5soc- clocking changes
> arradio/c5soc- interface updates
> arradio/c5soc- interface updates
> rfsom2/ccbox- rtc int
> rfsom/ccbox- rtc int
> rfsom2/ccbox- tsw s5 fix
> rfsom2/ccbox- tsw updates
> rfsom/ccbox- tsw updates
> daq2: daq2_qsys.tcl: Use sys_dma_clk
> jesd204: tx_ctrl: Fix status_sync assignment
> jesd204: jesd204_up_sysref: Remove unused signals
> jesd204: jesd204_up_common: Add missing core_cfg_transfer_en declaration
> jesd204: axi_jesd204_up_rx_lane: Fix padding signal width
> jesd204: Add names for generate for-blocks
> axi_dmac: request_arb: Add missing req_gen_{valid,ready} signal declaration
> axi_dmac: Update to verilog-2001 coding style
> axi_dacfifo: Fix port width at axi_dacfifo_wr
> adrv9371x: Write parameter as hexa value to clear Vivados ambiguity between decimal and binary
> jesd204: Update constraints for tx register map
> daq3/zc706: Fix system_top instantiation
> axi_xcvrlb: Fix util_adxcvr_xch instantiation (6d4430)
> axi_dacfifo: Fix axi_dlast generation
> axi_dacfifo: Few cosmetic changes
> axi_dacfifo: Increase the width of axi_last_beats and wvalid_counter
> plddr3_dacfifo_bd: Increase the AXI burst length to max
> axi_dacfifo: Define DMA/DAC_MEM_ADDRESS as parameter
> axi_dacfifo: DAC side CDC fifo control update
> axi_dacfifo: Add gray coder/decoder module
> ad_axis_inf_rx: Delete redundant local paramter
> axi_dacfifo: Fix the dma_ready signal generation
> fmcjesdadc1: vc707: Remove unsed mb_intrs signal
> Connect JESD204 interrupts
> axi_logic_analyzer: Streaming flag initial commit
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
