iio: adc: ad4630: Make fetch trigger PWM phase smaller than period

The ad4630 driver was implementing zone 2 data read by setting the fetch
trigger phase as the PWM period plus the conversion quiet time
(tquiet_cnv_delay).
However, the PWM driver may divide the phase value by the period time
length reducing any phase value higher than the period to zero. That
happens with the axi-pwmgen driver which is used with most ad4630 setups.

Interestingly, the PWM documentation (Documentation/driver-api/pwm.rst)
says the phase value must be lower than period in the sysfs interface
section. Although, not every PWM driver checks for that relation.

Change the fetch trigger PWM phase to be only tquiet_cnv_delay so the fetch
trigger phase offset is smaller than the PWM period.

Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>

Author: machschmitt

drivers/iio/adc/ad4630.c

@@ -94,6 +94,7 @@
 /* sequence starting with "1 0 1" to enable reg access */
 #define AD4630_REG_ACCESS		0x2000
 /* Sampling timing */
+#define AD4630_TQUIET_CNV_DELAY_PS	9800
 #define AD4630_MAX_RATE_1_LANE		1750000
 #define AD4630_MAX_RATE			2000000
 
@@ -406,7 +407,7 @@ static int __ad4630_set_sampling_freq(const struct ad4630_state *st, unsigned in
 	 * tsync + tquiet_con_delay being tsync the conversion signal period
 	 * and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly.
 	 */
-	fetch_state.phase = fetch_state.period + 10;
+	fetch_state.phase = AD4630_TQUIET_CNV_DELAY_PS;
 
 	return pwm_apply_state(st->fetch_trigger, &fetch_state);
 }
@@ -599,7 +600,7 @@ static int ad4630_update_sample_fetch_trigger(const struct ad4630_state *st, u32
 	pwm_get_state(st->conv_trigger, &conv_state);
 	pwm_get_state(st->fetch_trigger, &fetch_state);
 	fetch_state.period = conv_state.period * 1 << avg;
-	fetch_state.phase = fetch_state.period + 9800;
+	fetch_state.phase = AD4630_TQUIET_CNV_DELAY_PS;
 
 	return pwm_apply_state(st->fetch_trigger, &fetch_state);
 }